Abstract—Fat-tree networks have been widely used in the field of Network-on-Chip. One of the key issues in a fat-tree network is that the degree of a node has to be increased rapidly from the bottom of the tree to the root. As such, the complexity of implementing the switches near the root could be extremely high, and this poses a serious scalability issue. To cope with the scalability issue in fat-tree networks, many previous works require changing the tree topology and adding buffers in nodes. Unlike the existing arts, we adopt a different approach that can still maintain the original tree topology without adding any buffers in internal nodes. Our key idea is to explore various nice features of the load-balanced Birkhoff-von Neumann switc...
A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention...
The past few years have seen a rise in popularity of massively parallel architectures that use fat-t...
High-speed interconnection networks are essential elements for different high-performance parallel-c...
The development of ATM (Asynchronous Transfer Mode) switches is one of the main tasks required to i...
Load balanced Birkhoff-von Neumann (LB-BvN) packet switches have low hardware complexity while achie...
[[abstract]]Motivated by the need of a simple and high performance switch architecture that scales u...
[[abstract]]© 2002 Elsevier-Motivated by the need for a simple and high performance switch architect...
This paper presents an algorithm to automatically design two-level fat-tree networks, such as ones w...
Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low...
Abstract: This study proposes a scalable and cost effective Network on Chip (NoC) based architecture...
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper pr...
This paper shows that a novel network called the fat-stack is universally efficient when adequate ca...
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper pr...
We introduce orthogonal fat-trees as a type of interconnection network for parallel computers, and s...
In this paper we present a novel ATM switch called Parallel-Tree Banyan Switch Fabric (PTBSF) that c...
A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention...
The past few years have seen a rise in popularity of massively parallel architectures that use fat-t...
High-speed interconnection networks are essential elements for different high-performance parallel-c...
The development of ATM (Asynchronous Transfer Mode) switches is one of the main tasks required to i...
Load balanced Birkhoff-von Neumann (LB-BvN) packet switches have low hardware complexity while achie...
[[abstract]]Motivated by the need of a simple and high performance switch architecture that scales u...
[[abstract]]© 2002 Elsevier-Motivated by the need for a simple and high performance switch architect...
This paper presents an algorithm to automatically design two-level fat-tree networks, such as ones w...
Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low...
Abstract: This study proposes a scalable and cost effective Network on Chip (NoC) based architecture...
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper pr...
This paper shows that a novel network called the fat-stack is universally efficient when adequate ca...
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper pr...
We introduce orthogonal fat-trees as a type of interconnection network for parallel computers, and s...
In this paper we present a novel ATM switch called Parallel-Tree Banyan Switch Fabric (PTBSF) that c...
A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention...
The past few years have seen a rise in popularity of massively parallel architectures that use fat-t...
High-speed interconnection networks are essential elements for different high-performance parallel-c...