Cell Selection from Technology Libraries for Minimizing Power

In this paper we present a new library-oriented cell selection approach to minimize power consumption of combinational circuits. We formulate the low power cell selection problem as a Mixed Integer-Linear-Programming (MILP) problem. Cells with dierent sizes, supply voltages, and threshold voltages, can be selected simultaneously by our unied approach. Level shifter insertion required by supply voltage scaling is integrated into the cell selection process and the eect of insertion positions on power consumption is investigated. We put special eorts to reduce the size of the MILP and present eÆcient and eective heuristics to solve the MILP in short CPU time. Experiments are conducted on ISCAS'85 benchmark circuits. A 0.5 CMOS library from IBM is used as the technology library. Comparing with other approaches which select cells with one or two kinds of variations, our approach achieve 9 % to 26 % more power saving in 30 % to 79 % less CPU time.