, Rakibul Islam

Abstract: Reversible logic circuits are increasingly used in power Minimization having applications such as low power CMOS Design, optical information processing, DNA computing, Bioinformatics, quantum computing and nanotechnology. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. In the present paper an optimized and low quantum cost reversible multiplier using BME and Peres reversible logic gates is proposed. The proposed work is best compared to the other in terms of number of reversible gates and number of garbage outputs