A Unifying Interface Abstraction for Accelerated Computing

Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low-power FPGA, the peak computational performance of a sensor node can be improved without significant degrada-tion of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/soft-ware codesign for sensor node application development. We present the integration of nesC, a sensornet programming language, with GEZEL, an easy-to-use hardware description language. We describe the hardware/software interface at different levels of abstraction: at the level of the design lan-guage, at the level of the co-simulator, and in the hardware implementation. We use a layered, uniform approach that is particularly suited to deal with the heterogeneous inter-faces typically found on small embedded processors. We illustrate the strengths of our approach by means of a pro-totype application: the integration of a hardware-accelerated crypto-application in a nesC application. 1