Power vs. delay in gate sizing: Conicting objectives

The problem of sizing gates for power-delay tradeos is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimiza-tion problem is formulated using notions of convex program-ming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimum-power circuit is not necessarily the minimum-sized circuit.