VLSI Architecture for Optimized Low Power Digit Serial FIR Filter using MCM

Abstract:- Many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation that dominates the complexity of Digital Signal Processing (DSP) systems. On the other hand, digit-serial architectures offer alternative low-complexity designs, since digit-serial operators occupy less area and are independent of the data word length. This paper introduces the problem of designing a digit-serial MCM operation with minimal area at gate-level and presents the exact formalization of the area optimization problem In this paper, we address the problem of optimizing the area using multiple constant multiplier, design architecture. The proposed optimization algorithm is used in the design of digit-serial finite impulse response filters that will yield better performance, with high efficiency