Add to ORKGBased on voltage-to-time conversion technique, a pseudo-differential two-way-interleaved adaptive linear receive equalizer with two 2x-oversampled feed-forward taps has been designed in a 90 nm CMOS process. It integrates equalization and phase interpolation functions into one unit to simultaneously address inter-symbol-interference (ISI) cancellation and phase synchronization in a link receiver. It operates at 4 Gbps with 8 mW power consumption, and linearity of 4.3 effective bits at 1.2 V supply
As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are mo...
Abstract—This paper presents a 90-nm CMOS 10-Gb/s trans-ceiver for chip-to-chip communications. To m...
This paper presents a transceiver for fast and energy-efficient global on-chip communication, consis...
link to article page on IEEEBased on voltage-to-time conversion technique, a pseudo-differential two...
Abstract—Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective...
Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin eff...
process is described. A number of broadbanding and calibration techniques are used, which allow high...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
grantor: University of TorontoAn adaptive equalization system for data transmission over ...
This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver a...
An equalizer circuit which minimizes both crosstalk and ISI is applied to a receiver with a strongly...
The explosion of personal devices that need ubiquitous connectivity is making both wireless and wire...
This book introduces readers to the design of adaptive equalization solutions integrated in standard...
In high-speed (10+Gb/s) chip-to-chip links, the primary impairments to signal integrity are noise, c...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are mo...
Abstract—This paper presents a 90-nm CMOS 10-Gb/s trans-ceiver for chip-to-chip communications. To m...
This paper presents a transceiver for fast and energy-efficient global on-chip communication, consis...
link to article page on IEEEBased on voltage-to-time conversion technique, a pseudo-differential two...
Abstract—Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective...
Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin eff...
process is described. A number of broadbanding and calibration techniques are used, which allow high...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
grantor: University of TorontoAn adaptive equalization system for data transmission over ...
This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver a...
An equalizer circuit which minimizes both crosstalk and ISI is applied to a receiver with a strongly...
The explosion of personal devices that need ubiquitous connectivity is making both wireless and wire...
This book introduces readers to the design of adaptive equalization solutions integrated in standard...
In high-speed (10+Gb/s) chip-to-chip links, the primary impairments to signal integrity are noise, c...
A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation (DPWM) to...
As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are mo...
Abstract—This paper presents a 90-nm CMOS 10-Gb/s trans-ceiver for chip-to-chip communications. To m...
This paper presents a transceiver for fast and energy-efficient global on-chip communication, consis...