Speed ML MAP Processor Design for Dual Mode Binary Turbo Decoders

Abstract—This paper presents the Max Log Maximum a Posteriori (MAX Log MAP) architecture which influences maximum error correcting capacity and minimum hardware complexity. In Turbo decoding the design of Log MAP algorithm is complicated due to the exponential factor in the Log Likelihood Calculation. In this paper, a new architecture is designed based on jacobian logarithm which has a max function with the exponential correction factor. The complexity in the jacobian logarithm is further reduced by the Max Log Map algorithm by eliminating the correction term. Here Multistep Log Map algorithm is used for the approximation of the correction function. Furthermore a Dual Mode Single Binary and Double Binary (SB/DB) procedure is also used to compute the log likelihood ratio in order to reduce the hardware complexity and increase the speed of the computation. This method is implemented by XCS3S500E FPGA processor to achieve a High Speed 15 % to 25 % (as in existing); with less area Utilization (8 % as in existing) and low Power (74.95mW).The decoder throughput can be maintained in the proposed scheme without degrading the BER performance