NASA CR-121106 TRW 21083-6001-RU-00 . 0l . ASDTIC CONTROL t, W H tv - STANDARDIZED INTERFACE CIRCUITS APPLIED TO n BUCK, PARALLEL AND BUCK-BOOST . ° DC TO DC POWER CONVERTERS o Prepared for I by NASA Lewis Research Centerd Y. Yu Contract NAS3-14392 TRW SYSTEMS NATIONAL AERONAUTICS AND SPACE ADMINISTRATION INFORMATION SERVICE NASA Lewis Research Center https://ntrs.nasa.gov/search.jsp?R=19740008693 2020-03-23T10:53:29+00:00Z NASA CR-121106 TRW 21083-6001-RU-00 ASDTIC CONTROL AND STANDARDIZED INTERFACE CIRCUITS APPLIED TO BUCK, PARALLEL AND BUCK-BOOST DC TO DC POWER CONVERTERS by A. D. Schoenfeld and Y. Yu TRW SYSTEMS Prepared for NATIONAL AERONAUTICS AND SPACE ADMINISTRATION NASA Lewis Research Center Contract NAS3-14392 1. Report No. 2. Government Accession No. 3. Recipient's Catalog No. NASA CRI21106 TRW21083-6001-RU-OO0 4. Title and Subtitle 5. Report Date ASDTIC CONTROL AND STANDARDIZED INTERFACE CIRCUIT APPLIED February 1973 TO BUCK, PARALLEL, AND BUCK-BOOST DC TO DC POWER CONVERTERS 6. Performing Organization Code 7. Author(s) 8. Performing Organization Report No. A. D. Schoenfeld and Y. Yu 10. Work Unit No. 9. Performing Organization Name and Address TRW Systems Group Redondo Beach, California 90278 11. Contract or Grant No. Control and Power Electronics Department NAS3-14392 13. Type of Report and Period Covered 12. Sponsoring Agency Name and Address FINAL REPORT National Aeronautics and Space Administration Aug 1971 through Nov 1972 Lewis Research Center 14. Sponsoring Agency Code Cleveland, Ohio 44135 15. Supplementary Notes Project Manager, Vincent R. Lalli NASA Lewis Research Center Cleveland, Ohio 44135 16. Abstract Versatile standardized pulse modulation nondissipatively regulated control and control signal processing circuits were applied to three most commonly used dc to dc power converter config- urations: the series switching buck-regulator, the pulse modulated parallel inverter, and the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. .New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency. Three demonstration models for each of the three types of dc to dc converters were built, tested, and delivered to NASA/LeRC. 17. Key Words (Suggested by Author(s)) 18. Distribution Statement Buck-Boost Converter Series Switching Buck-Regulator Converter Pulse Moidulated Parallel-Inverter Converter Unclassified-unlimited Standardized Regulation Control (ASDTIC), and Digital Control Signal Processor (DCSP) DC-DC Converters 19. Security Classif. (of this report) 20. Security Classif. (of this page) 21. No. of Pages 22. Price* Unclassified Unclassified 127 * For sale by the National Technical Information Service, Springfield, Virginia 22151 NASA-C-168 (Rev. 6-71) FOREWORD This development project was sponsored under contract NAS3-14392 from the National Aeronautics and Space Admin- istration. For the support and technical interface provided by NASA, we would like to acknowledge Mr. V. R. Lalli of the Lewis Research Center, the NASA Project Manager. Our appreciation also goes to Dr. F. C. Schwarz, formerly of NASA/LeRC, who laid the foundation for this development and provided technical monitoring at the early contract stage. Special thanks are due Mr. J. J. Biess of TRW Systems, whose invaluable advice at the beginning of the contract on overall system design concepts contributed significantly to the success of this development. IIi TABLE OF CONTENTS Page 1. SUMMARY.......................................... 2. INTRODUCTION ................ .. ........................... 2 3. SWITCHING REGULATOR CONTROL PHILOSOPHY .................... 6 3.1 General Switching-Regula or Control System Block Diagram ....................................... 6 3.2 Category of Single-Loop Control Methods and Their Inherent Limitations........................... 8 3.3 History of Two-Loop Contol .......................... 10 4. STANDARDIZED ANALOG CONTROL SIGNAL PROCESSOR (ACSP)........ 12 4.1 Original ASDTIC Implementation....................... 12 4.2 ASDTIC Concept Used to Implement a Standardized ACSP.................................... 13 4.3 Inherent Merits of the Standardized ACSP............. 15 5. STANDARDIZED DIGITAL CONTROL SIGNAL PROCESSOR (DCSP) ...... 19 6. ASDTIC-CONTROLLED POWER CONVERTER DESIGN GUIDELINES....... 22 6.1 Power Circuit Design Guidelines...................... 22 6.2 Control Circuit Design Guidelines.................... 24 6.3 Brassboard Converter Package Design Guidelines........................................... 25 7. CONVERTER SPECIFICATIONS AND BLOCK DIAGRAMS............... 26 7.1 Converter Specifications............................. 26 7.2 Converter Block Diagram.............................. 29 8. POWER AND CONTROL CIRCUIT DESCRIPTIONS.................... 33 8.1 Converter Schematics................................. 33 8.2 Power Circuit Description............................ 33 8.3 Control Circuit Description.......................... 33 Preceding page blank TABLE OF CONTENTS I (Cont'd) Page 9. CONVERTER FABRICATION .................................... 43 9.1 General Mechanical Design Features................... 43 9.2 Converter Outline', Interface, and Weight............. 45 9.3 Converter Assembly and Subassembly ................... 46 9.4 Test Points. ............................... 50 10. CONVERTER STEADY-STATE PERFORMANCE ........................ 51 10.1 Output Voltage Regulation........................... 56 10.2 Efficiency.......................................... 57 10.3 Output Current Regulation.......................... 57 10.4 Output Voltage Ripple................................ 58 10.5 Source-Current Ripple............................ ... 58 10.6 Audio Susceptibility ................................ 59 10.7 Output Impedance.....................................61 10.8 Input/Output Isolation....................... ....... 63 10.9 Summary of Comparison Between Performance and Requirements.................................... 63 10.10 Discussion of Results................................ 63 11. CONVERTER TRANSIENT PERFORMANCE ........... 66 12. RECOMMENDATION FOR FUTURE WORK ........................... 77 13. CONCLUSIONS"............................................ 79 13.1 Power Circuit Technology Improvement................ 79 13.2 Control Circuit Standardization ..................... 80 13.3 Performances..................................... 80 vi TABLE OF CONTENTS (Cont'd) Page APPENDIX A SMALL SIGNAL ASDTIC OPEN-LOOP FREQUENCY RESPONSE............................................ 82 APPENDIX B MINIMUM-WEIGHT TOROID-CORE INDUCTOR DESIGN EQUATIONS.................................... 86 APPENDIX C PARALLEL INVERTER TWO-CORE TRANSFORMER DESIGN.............................................. 93 APPENDIX D A TWO-STAGE INPUT FILTER WITH NONDISSIPATIVELY- CONTROLLED DAMPING.................................. 96 APPENDIX E POWER AND CONTROL CIRCUIT COMPONENTS AND PARAMETERS.......................................... 103 El POWER CIRCUIT COMPONENTS AND PARAMETERS......... 103 E2 CONTROL CIRCUIT COMPONENTS AND PARAMETERS........ 104 APPENDIX F DESIGN CRITERIA AND DESCRIPTION OF POWER CIRCUIT FUNCTIONAL BLOCKS........................... 105 APPENDIX G DESIGN CRITERIA AND DESCRIPTION OF CONTROL CIRCUIT FUNCTIONAL BLOCKS........................... I 1 GI ASDTIC VOLTAGE REGULATOR........................ Ill G2 ASDTIC CURRENT REGULATOR........................ 113 G3 INPUT/OUTPUT ISOLATION AND SERIES REGULATOR....................................... 115 G4 DIGITAL CONTROL SIGNAL PROCESSOR (DCSP)......... 116 G5 PARALLEL-INVERTER CONVERTER PROTECTION CIRCUIT......................................... 121 APPENDIX H NOMENCLATURES....................................... 123 REFERENCES........................................................ 125 vii LIST OF FIGURES Page Figure 1. A Generalized Converter Control Circuit Block Diagram. . ...... . ............ . 7 Figure 2. Original ASDTIC Implementation. .......... . 14 Figure 3. Modified ASDTIC Implementation . . . .. .... . 14 Figure 4. Adaptive Duty-Cycle Control Waveform. . ... . .. 16 Figure 5. Standardized Digital Control Signal Processor (DCSP). . ................ . 20 Figure 6. Power Configurations of the Three Demonstration Converter Models. .......... . 27 Figure 7. A Common Block Diagram for All Three Converters. . . . . . . . . . . . . . . .. . . . . 30 Figure 8. Schematic Diagram of the Buck-Boost Converter. . ................ .. 34 Figure 9. Schematic Diagram of the Series-Switching Buck Regulator .................. .35 Figure 10. Schematic Diagram of the Pulse-Modulated Parallel-Inverter Converter ......... . .. . . . . . .36 Figure 11. Buck-Boost Converter Configuration and Waveform. ...... ................ . . . . . . . . 37 Figure 12. Series Switching Regulator Configuration and Waveform. . ...... . .......... . . . 38 Figure 13. Parallel-inverter Converter Configuration and Waveform. ... ........ . . . . . . .. 41 Figure 14. Buck-Boost Converter Brassboard Configuration. . . .47 Figure 15i Series Switching Regulator Brassboard Configuration . . . . . . . . . . . . . . . . . . . 48 Figure 16. Parallel-Inverter Converter Brassboard Configuration .... ............. . . . 49 viii Page Figure 17. Regulator and Digital Control Signal Test Points. . ....... ............ . . 50 Figure 18. Measured Audio-Susceptibility Performance. ..... 60 Figure 19. Measured Output Impedance .............. .62 Figure 20. Transients During Converter Command On. . ...... .70 (Output at Full Load) Figure 21. Transients During Converter Command On. . ...... .71 (Output Load Short Circuited) Figure 22. Transients During Converter Turn-On By a Step Application of Input Voltage . . ..... . 72 Figure 23. Transients During Sudden Converter Output Short Circuit. . . . . . . . . . . . . . ...... . 73 Figure 24. Transients During Removal of an Output Short. . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 25. Transients During Step Input Voltage Change . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 26. Transients During Step Load Change. . ........ .76 Figure 27. Block Diagram of ASDTIC-Controlled Series Switching Buck Regulator .. . . . . . . . . .83 Figure 28. Open-Loop Frequency Response of the ASDTIC Control . . . . . . . . . . . . . . . . . . . 85 Figure 29. Input-Filter Frequency Response With and Without the Reflected Negative Resistance From the Converter Regulator ............ .102 Figure 30. Buck-Boost Converter Power Transistor Switching Patterns With and Without the Energy Recovery Network. . ............ .109 Figure 31. S2ries Switching Buck Regulator Power Transistor Switching Pattern With and Without the Energy Recovery Network. . ...... .. 109 ix LIST OF TABLES Page Table I. Summary of DC to DC Converter Specifications. ..... .28 Table 2. Summary of Power Circuit Functions. . ........ .31 Table 3. Summary of Control Circuit Functions. .... . . ....32 Table 4. Basic Buck-Boost Power Configuration. . . . . . . . .37 Table 5. Basic Series Switching Buck Regulator Configuration ... ... .... . ......... . 39 Table 6. Basic Parallel-inverter Converter Configuration . . . . . . . . . . . . . . . . . . . .41 Table 7. Summary of Converter Size, Interface and Weight. ...... . .... . ......... 45 Table 8. Steady-State Performance Data for Buck- Boost Converter . ..... ..... ....... . . 52 Table 9. Steady-State Performance Data for Series- Switching Buck Regulator . . ... . .. . . . . . . . .53 Table 10. Steady-State Performance Data for Pulse- Modulated Parallel-Inverter Converter ........ .54 Table 11. Summary of Output Voltage Regulation. . ... .... . .56 Table 12. Summary of Converter Efficiency at full Load and Room Temperature .......... . . . . .57 Table 13. Summary of Output Regulation. ........... . . . .58 Table 14. Summary of Output Voltage Ripple. . ....... .. 58 Table 15. Requirements Versus Capabilities of Prototype Converters. . . . . . . .. .. . . . . . . 64 Table 16. Power Circuit Components and Parameters . ..... !103 Table 17. Control Circuit Components and Parameters . . . . . 104 x 1. SUMMARY The application of versatile pulse modulation control and control signal processing circuits to the three most commonly used nondissipa- tively regulated dc to dc converter power circuit configurations: the series switching buck regulator, the pulsewidth modulated parallel inverter, and the buck-boost converter, is discussed in detail. The Analog Signal to Discrete Time Interval Converter (ASDTIC), conceived originally within NASA, was utilized as the Standardized Analog Control Signal Processor (ACSP) of the three dc to dc converter regulators. The application has resulted in uniformly superior static and dynamic per- formance for all three types of dc to dc converters. Commonality of control signal functions for all switching regu- lators,made possible by the ASDTIC and the newly developed Digital Control Signal Processor (DCSP) circuits, has resulted in control-circuit standard- ization of the three dc to dc converters. New power-circuit technology, including component stress control and recovery of power transistor switching loss, was applied to improve reliability and to optimize weight and efficiency. Three demonstration models for each of the three types of dc to dc converters were built, tested, and delivered to NASA LeRC. The static and dynamic performance of the demonstration models, as well as the power component stress control philosophy implemented in their design, has greatly advanced the state-of-the-art in the design of dc to dc converters. 2. INTRODUCTION A nondissipatively-regulated dc to dc converter generally achieves efficient voltage transformation and regulation through cyclic operation of its power switch in alternate conduction and nonconduction states, Consequently, the converter control system must be able to converter analog signals derived from the converter output and the control reference, through an A-to-D process, into discrete time intervals in controlling the on-off duty cycle of the power switch. The modulated pulse train derived from the cyclic operation of the power switch is then converted back, through a D-to-A process, to analog form at the converter output by a low-pass filter. Converter output regulation can be achieved through modulation of the power switch on-time (T ) and/or off-time (Tf). A pulse modulation for voltage or current regulation of dc to dc con- verters can be implemented through numerable control circuits proposed and in use today. Generally speaking, they can be categorized into two types of feedback control mechanization: (1) single-loop feedback control and 2) multtple loop feedback control. The electrical performance of a dc to dc converter depends, to a large extent, on the quality of its control system. Unfortunately, most single-loop approaches suffer from many inherent limitations: S Due to the presence of a second-order LC filter for output ripple reduction, the utilization of a high gain and wider band width amplifier necessary for good static regulation, high audio-susceptibility reduction, and fast dynamic re- sponse is usually accompanied by an increasing risk of dynamic instability induced by line or load changes and variations in component characteristics due to component tolerances, envir- onmental effects, and aging. * The long time constant associated with the low-pass filter delays the rate of power-switch-modulation adjustment respond- ing to a dynamic line and/or load disturbance, thus compromising the converter dynamic response. * Due to the many transport delays including the power transistor storage time, additional loop gain is needed to reduce the error, which again leads to an increasing risk of instability. 2 The stringent demands of space and military programs have served to promote considerable research effort toward the development of an electronic control system capable of mitigating these limitations. One such system was conceived and disclosed through a NASA Internal Research Program. [1,2] The system utilizes a multiple-loop control mechanization. The controlling element is basically an Analog-Signal-to-Discrete-Time-Interval-Converter (ASDTIC), which was subsequently reduced to a microminiaturized thin film hybrid module. Since then, the ASDTIC module has been employed in dif- ferent types of nondissipative regulator applications, with the static reg- ulation and dynamic performances approaching those generally exhibited only by dissipative regulators. The basic objectives of this program were to develop and demonstrate the application of ASDTIC to the three most commonly used dc to dc converter power circuit configurations and to develop the associated control signal processing circuits. The successful performance of this program did lead to the following achievements: * Verify and demonstrate the application of the ASDTIC control system to three distinct and functionally different types of dc to dc converter power circuit configurations: Buck-Boost Converter Series Switching Buck-Regulator Pulse Modulated Parallel-Inverter * Design and development of interface circuitry between the ASDTIC control element and the power circuits of the respective dc to dc converters. These control signal processing circuits should exhibit commonality among different converters to further standardization. * Accomplishment of superior performance characteristics including superb static and dynamic output characteristics and input current inrush limiting (for the prevention of the collapse of current limited primary power sources). * Construction, testing, and delivery of one breadboard and two brassboard demonstration models for each of the three types of dc to dc converters. 3 In accordance with the contract, the program proceeded sequentially through the following phases: Task 1: Technical Plan Task 2: Converter Development and Design Task 3: Converter Fabrication and Test A Technical Plan summarizing results of Task 1, 15was used to guide the efforts of Task 2. A report, prepared at the conclusion of Task 2 served as a construction plan for the three regulator converters. One breadboard and two brassboard demonstration models of each converter type were subsequently built and tested to establish their compliance with the technical specifications. The demonstration models were delivered to NASA/LeRC. This report presents the pertinent information generated in the course of the three tasks performed over a period of one year starting in September 1971. The presentation starts with a general switching-regulator converter control block diagram presented in Section 3, from which ASDTIC concept is evolved. Using ASDTIC as the standardized Analog Control Signal Proc- essor, a qualitative discussion of ASDTIC then follows in Section 4, which highlights its salient features. To complete the control-circuit standardization, a Digital Control Signal Processor (DCSP) is described in Section 5. The design guidelines for the power and control circuits of the three aforementioned dc to dc converters are presented in Section 6. The three converter block diagrams, featuring the commonality of func- tional blocks, are given in Section 7, followed by circuit descriptions in Section 8. The construction of the demonstration models of the three types of dc to dc converters is discussed in Section 9. The static and transient performance data are included in Sections 10 and 11, respectively. Recom- mendation for future tasks is presented in Section 12, and the report ends with conclusions in Section 13. To anyone working with nondissipatively regulated dc to dc converters, certain design intricacies inevitably make themselves felt throughout the converter design and development stage. While by no means intended as a final solution to an optimum converter design, the work described herein nevertheless represents a step forward in an effort to bring into sharp focus the converter system design philosophy as well as its functional standardization. Specifically, the effort resulted in the following key achievements: (1) The control system implementation through standardized control and interface circuits including both standard- ized analog and digital-control signal processors. These circuits can be applied to all types of switching regulators using either transistors or SCR's as power switches. (2) The successful application of the standardized control system to the three most commonly used dc to dc converters: (A) the energy-storage buck-boost converter, (B) the series- switching buck regulator, and (C) the pulse-modulated paral- lel-inverter converter. The static regulation and dynamic performance of each converter were demonstrated to approach the high levels generally exhibited only by dissipative regulators. (3) Active power-component stress control under all conceivable transient operations was facilitated by a peak-current sensor and the standardized digital control signal processor, thus enhancing the reliable operation of each converter. (4) Optimum weight-efficiency was made possible by: (A) energy- recovery networks to minimize the switching losses in the power switch, (B) an active magnetics-saturation sensor to eliminate saturation current in the parallel-inverter trans- former, (C) a set of well-conceived power magnetics design equations, and (D) a proportional power switch base current drive. 5 3. SWITCHING REGULATOR CONTROL PHILOSOPHY As stated in Section 2, the analog signal at the output of a switching- regulator, after comparison with a reference, must be transformed into a digital signal to control the on-off duty cycle of the power switch. The controlled digital pulse train at the power switch output is averaged by an energy storage element and the analog control signal is derived from the regulated dc output of the dc to dc converter. The objective of this section is twofold. One is to present a general switching-regulator control system block diagram, from which the various conventional single-loop control methods are categorized, and their relative drawbacks reviewed. The second is to provide a brief history of two-loop control, from which the specific control system used in this program is evolved. 3.1 General Switching-Regulator Control System Block Diagram Generally speaking, the A-to-D-to-A process is accomplished, as shown in the block diagram of Figure 1, where a series switching converter is used for illustration purpose Starting with a signal at the converter output, i.e., point A of Figure I and tracing clockwise, the signal is processed by an Analog Control Signal Processor (ACSP) composed of a reference, an error amplifier, and a ramp function generator. After comparing the sensed signal to the ref- erence, the error is amplified by a properly-compensated amplifier, which results in a signal at point B. The amplified output is then either: (1) combined with, or (2) transformed into, a ramp function. The ramp can be a flux ramp via a magnetic device, or it can be a voltage ramp ob- tained, for example, by charging a capacitor. When the instantaneous ramp voltage reaches a threshold level, it causes the threshold detector output, point C of Figure 1, to change state. This change of state, in turn, actuates a Digital Control Signal Processor (DCSP) to control the turn-on or the turn-off of the power switch n. Voltage pulses with an amplitude POWER SWITCH Ei Q ENERGY A o0 STORAGE ELEMENT DIGITAL CONTROL SIGNAL C TIME PROCESSOR CONTROL (DCSP) RAMP FUNCTION S+ AMP- REF THRESHOLD ANALOG CONTROL SIGNAL PROCESSOR (ACSP) LEVEL Figure 1. A Generalized Converter Control Circuit Block Diagram corresponding to the input voltages E. are averaged by the energy storage element, thus closing the loop at its starting point, i.e., point A. This general control concept can be implemented through numerous circuits. The variations are primarily due to the different means through which the ramp function and the threshold level are mechanized. Notice the necessity of a ramp function intersecting a threshold level, for without it the transformation from the analog error at point B to a digital pulse train at point C and at the power switch output is impossible to initiate. Notice, also, the significance of the DCSP. Depending on how it is mechanized, the duty-cycle of the power switch can be controlled by the following combinations of on-time T and off-time Tf: (1) constant T ,n f n variable Tf, (2) constant Tf, variable Tn, (3) constant (Tn + Tf), variable T and Tf , and (4) variable (Tn + T f), variable T and T .n f n f n f 3.2 Category of Single-Loop Control Methods and Their Inherent Limitations Generally speaking, the intersection of the ramp and the threshold level in classical, single feedback loop control is achieved through either one of the three following implementations: (1) The ramp (or, the threshold level) at the ACSP output, generated from the amplified error, intersects a fixed threshold level (or, a fixed ramp) to actuate the DCSP. [7, 8, 9, 10, 11, 121 (2) The ramp or the threshold level is generated as an exclusive function of converter input voltage E.. When the ramp is line dependent, the threshold level is fixed. Likewise, a line dependent threshold level is complemented by a fixed ramp. The composite analog error and the ramp are compared to the threshold level to actuate the DCSP [13, 14] (3) The ramp is simply the ac ripple of the converter output voltage, E o. The error amplifier is essentially unity gain and there are two threshold levels corresponding to the peak and valley of the output ripple. The two threshold levels are combined with the DCSP to form a bistable hysteretic trigger. [15, 16, 17, 18] 8 Converters of category (1) derive the ramp or the threshold level from the output error exclusively. This method suffers from the follow- ing inherent limitations: o Due to the presence of a second-order LC energy storage element for output ripple reduction, the utilization of a higher gain and wider bandwidth ACSP amplifier necessary for good static regulation, high audio-susceptibility re- duction, and fast dynamic response is usually accompanied by an increasing risk of dynamic instability. The instability can be induced by line or load changes and variations in component characteristics due to component rating toler- ances, environmental effects, and aging. o The long time constant associated with the low-pass output filter delays the rate of power-switch-modulation adjustment responding to a dynamic line and/or load disturbance, thus compromising the converter dynamic response. o Due to the many transport delays including the power trans- istor storage time for all converters and power transistor on time T for certain types of converters, converter insta- n bility becomes imminent when a high gain, large bandwidth control is attempted. Consequently, the performance for converters of category (1) are inevitably compromised by the stability criterion. These inherent limita- tions are partially alleviated in converters of category (2). The static and dynamic regulation against line change is improved, in an open-loop fashion, by the line dependent ramp or threshold-level generation. However, static line regulation and converter stability are still degraded by trans- port delays, and the dynamic performance against load changes is again hamp- ered by the output energy storage element. Converters of category (3) represent a classical application involving a second-order system with hysteresis. Generally, their dynamic perform- ances are superior to those of categories (1) and (2). The output ripple itself is used as the ramp between two hysteretic levels, within which the dynamics against line and load distrubances are bounded. The simplicity and unconditional stability of the nonlinear control has lent itself to extensive modeling and analysis [15,17,19,20]. Its known functional subtleties include: (A) the heavy dependence of converter performance on the amount of equiv- alent series resistance (ESR) in the output filter capacitor, (B) the dc output voltage is a function of the transistor storage time and the output ripple waveform; its average value within the boundary of two hysteretic levels is not precisely controlled, (3) although its operating frequency range can be made small [21], it is still unable to engage in a constant frequency operation, which may be mandatory for applications involving frequency syn- chronization, and (4) thus far, the control has been applied only to the buck type switching regulators and their equivalent [21]. Up to this juncture, the common denominator of the three control categories discussed above is the utilization of a single feedback loop. 3.3 History of Two-Loop Control Confronted with such inherent limitations of the single feedback-loop switching regulator, multi feedback-loop regulation-control concepts were advanced. As early as 1964, patents [22,23] were filed in which a second feedback signal was applied to effectively reduce the hysteresis width of the bistable trigger, thus allowing a higher frequency of operation than otherwise feasible. A converter where both dc and ac information were in- cluded in its feedback loop by sensing the voltage in front of the filter inductor was reported [24], which resulted in stable operation of the con- verter over a relatively large change in output-filter capacitance. Another two-loop regulation control concept was developed in which the ramp is generated by reproducing the current in the output filter inductor [251. The ramp is then summed with the output of the error ampli- fier and is used in a closed loop fashion to control the on-off of the power switch through a bistable hysteretic trigger. Basically, this system closely resembles converters of category (3) in principle. The ramp generated from the inductor current is identical in waveform to the ripple across the output filter capacitor having a sufficient ESR. The converter, therefore, possesses the performance advantages of control category (3). However, by using the inductor current to replace the capacitor voltage as the ramp function, the converter operation no longer depends heavily on the capacitor ESR. Furthermore, the use of the additional feedback permits 10 the design of a high-gain dc loop for precision output voltage regulation. The technique also provides inherent current limiting. However, due to its two-state modulation, it is limited to performing duty cycle control at a constant off time, Tf. Still another regulation control concept employing an additional feed- back loop was conceived within a NASA Internal Research Program [1, 2]. Here the ramp function is generated by integrating the rectangular ac voltage at the power switch output. A modified version of this concept derives the ramp function by integrating the ac voltage across the filter inductor. The additional ac loop is responsible for improvements in static and dynamic converter performances. In conjunction with a fixed threshold level and the DCSP, the triangular integrator output is used as the ramp function to accomplish power switch duty-cycle control. This concept uses an Analog to Discrete Time Interval Converter (ASDTIC)for the ACSP and threshold detector functional blocks of Figure i [3, 4, 26J. The control is flexible, as it can be accomplished throuqh either a constant T , a constant Tf, a constant (Tn + T f), a line dependent T n, or a two-state mod- ulation. 11 4. STANDARDIZED ANALOG CONTROL SIGNAL PROCESSOR (ACSP) As described in Section 3, the modified ASDTIC derives the necessary ramp function by integrating the voltage across the filter inductor. In this section, the original implementation of the control concept is first described, which then leads to the modified version used in the present program. The inherent merits of ASDTIC are discussed with regard to its dynamic capability and stability, thus laying the foundation for a qualitative understanding of the high performance exhibited by the ASDTIC-controlled dc to dc converter- regulator. 4.1 Original ASDTIC Implementation. The ASDTIC control concept, originally conceived within NASA,[2] can be represented in Figure 2, where a series-switching converter is utilized for illustration. The filter inductor L is shown to have a dc resistance. Rdc. Voltages e.i and eo at either end of the inductor are divided down by a factor Kd, and compared with reference ER . Thus, the integrator input voltage contains error signals edc and eac, where edc = KdeO - ER, and eac = Kde -E The integrator is, in reality, a high gain dc amplifier with capacitor feedback. Consequently, edc is extremely small and /eac/>>edc holds, leaving the integrator input voltage, x, as that shown in Figure 2. The triangular integrator ac output, serving as the ramp function, is super- imposed on the amplified dc error to intersect a threshold level,ET. The intersection actuates the DCSP to perform the proper control of the power switch. This implementation was tested and found to yield excellent regulation against input-voltage variation. However, its performance against load change was hampered by resistance Rdc in the inductor winding. Qualitatively, the detrimental effect of Rdc to load regulation is understandable. Voltages e. and eo differ by a voltage drop across Rdc, yet both voltages are compared with the same reference ER to establish the dc error. The inner loop sensing e. is,therefore,interferring with the proper function of the outer loop sensing eo , which prevents a precision regulation for e . In the worst-case limit, when only the inner loop exists, the load regulation against a load- current change I° is R dcAl 12 4.2 ASDTIC Concept Used to Implement a Standardized ACSP. The modified ASDTIC concept was used in this program for the regula- tion control of three different types of dc to dc converters. The commonality facilitated the use and demonstrated the practicality of the standardized Analog Control Signal Processor (ACSP). The modified ASDTIC concept is represented in Figure 3. The error- processing component of the standardized ACSP is a high-gain error amplifier with a capacitor feedback, i.e., an integrator. Two input signals are applied to the integrator-amplifier through two feedback control loops. The first loop senses the dc output voltage eo of the converter, divides it by a factor Kd = 1, and compares Kdeo to the amplifier reference ER. The difference edc = Kd e - ER becomes the dc error input. In conjunction with a threshold-detector level ET, the dc output level of the integrator- amplifier is determined by edc. The second loop senses the ac component of (e.-e ) across the filter Inductor L , transforms it by a factor n 2 1, I 0 . < and feeds eac = n (e -e ) differentially to the integrator-amplifier. C I The rectangular ac voltage eac, along with the much smaller dc error edc' are integrated. The integrator triangular output, serving as the ramp function, is superimposed on the amplified dc error to intersect the threshold-level ET. The threshold detector actuates the Digital Control Signal Processor (DCSP) to control the duty cycle of power switch Q. Notice that, unlike Figure 2 in which the inner loop sensing e. handles both dc and ac information, the second loop of Figure 3 processes only the ac information for the purpose of ramp generation. It, therefore, no longer interferes with the dc regulating function of the first loop sensing eo. Experimentally, the modified ASDTIC of Figure 3 exhibited an order of magnitude improvement over that of Figure 2 insofar as the load regulation was concerned. As for the regulation against line change, the two systems offer essentially identical performances. Consequently, the system of Figure 3 was utilized in the present program. An additional feature not to be overlooked in the system concept of Figure 3 is its universal adaptability to all switching regulators. For as long as there exists within the regulator an inherent ac waveform suitable for ramp- function generation, the standardized ACSP can be conveniently applied to sense a dc voltage signal at any point in the converter. 13 r P~ ~n(ei-e ) o THRESHOLD DETECTOR Kd eC +d ER ACSPLR nc (e , - e ) t >t Figure 2. Original ASDTIC Implementation e. eo E ei Lo Rdc eC0o C O , DCSPKK THRESHOLD d d DETECTOR ACSP Kde Kdeo ER ET ER ERt K Tn - Tf T f ( ac FL_-' Figure 3. Modified ASDTIC Implementation 14 4.3 Inherent Merits of the Standardized ACSP As stated previously, the long time constant of the output energy- storage elements and the various transport lags often make it impossible to achieve simultaneously fast transient response, stability,and precis- ion regulation for a dc to dc converter employing a single-loop control. In this regard, the two-loop standardized ACSP using the ASDTIC regulation control concept offers the fbllowing merits: (1) Owing to the additional ac loop, the rate of change of the regulator duty cycle in responding to line disturbances is not limited by the relatively slow dc loop. The fast reaction can be verified by considering Figure 4 (A), in which the converter output voltage is regulated at e = E0, and sudden changes in input voltage are indicated to occur at tl, t2 , and t3. For clarification, the following conditions are assumed: (A) The DCSP is programmed for a constant "T " n operation. Each time an increasing ramp intersects the threshold level, it initiates the conduction of the power switch for a fixed time interval T , and the output voltage is regulated by controlling Tf. (B) The time constant of the output filter is much longer than a switching period (Tn + Tf), thus maintaining an essentially constant Eo within a switching period independent of any step change in e.. (C) All components are ideal and loss- less. Under these assumptions, the integrator and inductor volt- ages for Figure 4(A) are shown in Figure 4(B) and Figure 4(C), where T is constant as assumed. During T , the voltage across n n the inductor is e.-e , where e. is the step waveform of Figure 4(A) and e = E is the regulated output voltage. The slope of the o o integrator ramp during Tn is thus proportional to e. - e , while during Tf the slope is constant determined by Eo. Between t = 0 and t = tl, when e. = 2Eo , the steady-state oper- ation results in equal Tn and Tf, giving a duty cycle Tn/(Tn + Tf) = 0.5. When e.i is suddenly increased from 2Eo to 4E at t , which for clarity was made to coincide with the start of a new T , the steeper ramp slope proporational to 3E duringn o T now causes the ramp amplitude to be three times larger at the 15 ei e o (A) e o I e. =3E e. =2E 0 o eo = Eo l 2 3 t INTEGRATOR OUTPUT (B) THRESHOLD LEVEL t e2 (C) 3E E E 2E .-E I .- T 2Tf- T ITfJ Figure 4. Adaptive Duty-Cycle Control Waveform 16 end of T . It therefore takes a time interval of 3Tf before n the positive ramp can intersect the threshold again to start the next Tn, giving a new duty cycle of 0.25. Since the re- quired steady-state duty cycle is e /e i for this converter, the duty cycle becomes 0.5 and 0.25 when e i = 2eo and e = 4eo respectively. The correct duty cycle is adaptively achieved on an instantaneous basis without being delayed by the time constant of the output filter. Similarly, the auto-compensation effect for step input changes at t2 and t3 can be easily verified. (2) The regulator stability is immune to control component parameter Changes. The small-signal open-loop frequency response of this standardized ACSP is given in Appendix A. The analytical results show that the converter stability is not effected by changes in the output-filter configuration, the output loading, the error amplifier gain, the threshold level, the integrator time constant, and all other critical control parameters. The immunity reduces significantly the effort normally required in performing the worst-cast stability analysis. Such an analysis would be time consuming, as all parameter changes due to initial tolerances, temperature variation, and aging must be considered collectively. The immunity also provides a highly desirable feature for specific applications such as nuclear-harden- ing electronics, in which critical component parameters are known to undergo drastic changes. (3) High gain, wide bandwidth, and precision regulation against line and load changes. Analysis has also shown that the two-loop standardized ACSP can achieve high gain and stable operation concurrently. The open- loop dc gain is essentially that of the ACSP operational error amplifier, which is in the order of 100 db. The ac loop can be designed to eliminate the roll-off effect of the output filter, thus significantly increasing the bandwidth of the converter operating at a given switching frequency. These combined features are responsible for the good line and load regulation exhibited by the converters controlled by the standardized ACSP. 17 (4) Elimination of the detrimental effects of transport lags and other functional subtleties. Since the auto-compensation between Tn and Tf is achieved by sensing the inductor voltage, in which the power-switch storage time is treated as part of on-time,Tn, the effect of the storage time on the output regulation and line rejection is minimized. More important, the functional subtlety of certain converter types such as the buck-boost converter and the boost converter has made them most vulnerable to limitations of the single-loop control. The outputs of each of these converters are decoupled from the control-signal path during power-transistor on time T . The n consequences are: (1) As far as its feedback control loop sens- ing the output error is concerned, the entire on-time interval T n is equivalent to a transport lag, and (2) A low-frequency char- acterization of these converters has revealed a novel "positive- zero" term [27] in the frequency response of these converters. The two factors significantly limit the bandwidth of these con- verters w hen zcontrolled by a single-loop sensing only the output error. (5) Capability of controlling all switching regulators operated in different duty-cycle control modes. The standardized ACSP is applicable to all switching regulators capable of providing an ac waveform for ramp generation. The ramp at the output of the standardized ACSP can be used in con- junction with a single threshold level or a bistable hysteresis level so that the DCSP can be configured to achieve duty-cycle control using either a constant T , a constant Tf, a variable n f T and Tf with (Tn + Tf) constant, or a variable T and T withn f n f n f (Tn + Tf) also variable. The aforementioned advantages have been verified by the performance of the three different types of dc to dc converter demonstration models using the standardized ACSP. The application of the standardized ACSP was complemented by a standard- ized Digital Control Signal processor (DCSP), which is discussed in the next section. 18 5. STANDARDIZED DIGITAL CONTROL SIGNAL PROCESSOR (DCSP) Presented in this section is a novel DCSP which, in conjunction with the standardized ACSP described in Section 4, could form a universal control circuit for all dc to dc converters. The implementation of the standardized DCSP is shown in Figure 5. It is composed of two pulse stretchers, three NAND gates, and two R-S flip- flops. Each pulse stretcher gives an output pulsewidth equal to the sum of the input pulsewidth and a stretched time interval determined by external RC time constants. The digital outputs from flip-flop #2 are fed back directly as inputs to the respective pulse stretcher. The output at point Q is used to control the on-off times of the power switch through a driver whose output is proportional to the current in the power switch. The DCSP receives the following signals: (1) Converter Input Voltage Applied to R92. The converter voltage, E., along with R92, C92,and the internal-threshold level of pulse stretcher (2), determines the on-time interval Tn for the power switch. (2) Regulated Voltage Applied toR91. This voltage, along with R91, C91, and the threshold level inside pulse stretcher (1), deter- mines the minimum off-time T during transient operations. m (3) ACSP and Current Regulator Signals. By applying these regulator signals from the respective threshold detectors to NAND (1), digital signals in series with NAND (2) are not affected. Con- sequently, on time T , is not altered by the regulator function. n The regulating signals applied to NAND (1) therefore serve only to inhibit the turn-on of the power switch by extending the off-time interval beyond the programmed minimum off time, Tm' to achieve the required duty-cycle control. (4) ON-OFF Command Applied to NAND (3). A logical-O applied to NAND (3) causes its output to be logical-1; this condition corresponds to the off condition for the power switch. A logical-i applied to NAND (3) allows the DCSP to start the con- verter at a free-running frequency I/(Tn + Tm) until the output regulation level is reached. 19 FROM CURRENT FROM ONIOFF REGULATOR COMMAND 1 3 5 7 REGULATED E. R91 1C91 FROM ACSP R92 C92 FROM PEAKi CURRENT SENSOR PULSE STRETCHER (1) R-S FLIP FLOP (1) NAND (1) R-S FLIP FLOP (2) NAND (3) PULSE STRETCHER (2) NAND (2) Figure 5. Standardized Digital Control Signal Processor (DCSP) (5) Peak-Current Sensor Signal Applied to NAND (2). To limit the peak transient current in the power transistor switch requires that it be turned off before the normal T is timed out. The n early termination of Tn is accomplished by a logical-O input to R-S flip-flop #1 before the pulse-stretcher (2) output changes state. The signal is obtained from the peak-current sensor. The new standardized DCSP was developed with a total of only seven parts including three IC's, two capacitors, and two resistors. Furthermore, it is readily adaptable to different methods of duty-cycle control. The DCSP shown here, with converter input voltage E. applied to R92,is config- ured for a converter duty-cycle control based on a constant E.T , i.e., a In line-dependent variable on time Tn and a variable off time Tf. However, if an externally-generated constant voltage independent of varying E. were applied to R92, the DCSP would then produce a constant Tn and a variable Tf. If the feedback signals to the pulse stretchers were not from the outputs of the R-S flip-flop (2), but were from the flip-flop (1), then both Tn and Tf would vary, yet the sum of Tn and Tf would be kept constant, resulting in constant-frequency operation. An external clock (with a frequency higher than the free-running frequency of the DCSP) applied to flip-flop (1) would result in synchronization of the converter switching frequency with the clock frequency. From these descriptions, the following advantages offered by this standardized DCSP become evident: (1) circuit simplicity, (2) performance of multiple functions and ease of interfacing including control, command, protection and orderly converter startup, (3) flexibility of adapting to various switching regulators, and (4) versatility of the cir- cuit to perform duty-cycle control at either constant T , constant Tfn f constant Tn + Tf, or a line-dependent T . 21 6. ASDTIC-CONTROLLED POWER CONVERTER DESIGN GUIDELINES The objectives of this program were to demonstrate the application of the standardized Analog Control Signal Processor (ACSP) to three most used dc to dc converter configurationsand to develop a Digital Control Signal Pro- cessor (DCSP) which, in conjunction with the ACSPwould be used as a universal control circuit for the regulation and control of any dc to dc converter. In the process of the design and development of the demonstration models for the three types of dc to dc converters, new power circuit tech- nology was applied to improve reliability and to optimize weight and efficiency. To achieve these objectives, certain guidelines were established. The design guidelines used in this program and their rationale are discussed below. 6.1 Power Circuit Design Guidelines (1) High Reliability through Component Stress Control. One of the most lagging aspects of power processing technology at present is that of reliability. By this is meant the failure to consistently achieve in opera- tional equipment the reliability that one might anticipate from consideration of the reliability of the components themselves. The reliability of the power converters can be greatly enhanced by controlling the power component stresses during steady state and, more important, during dynamic operations such as step line and/or load changes, sudden output short circuit, and converter starting. The power switch is the single most vulnerable and important power component, whose operation also determines the stress level of essen- tially all other power components. For this reason, a peak current sensor, which turns off the switch as soon as the switch current exceeds a certain limit, and an energy-recovery network, which minimizes the stresses and the switching loss in the power switch, shall be implemented for each converter [28]. (2) Optimum Weight Efficiency Tradeoff. Aside from reliability, weight and efficiency are the two other major concerns in the designing of power converters. To achieve a balance between weight and efficiency, the following guidelines were adopted: 22 (A) Converters processing large line and load variations should be designed to pass a trapezoidal power-switch current at heavy load, and a triangular current at light load. In other words, the power inductor should be designed to exhibit a critical inductance at an intermediate load. (B) The power magnetics contribute to a majority of the total converter weight as well as significant portions of the total converter loss. Their design must be guided by a set of carefully derived design equations. See Appendix B. (C) To maintain high efficiency at light load, the utilization of a proportional base-collector current drive is necessary. (D) The aforementioned energy-recovery networks should be used to prevent the overlap of high voltage and high current associated with the power switch during its switching intervals, thus improving the efficiency and eliminating the possibility of secondary breakdown. (E) High current spikes resulting from saturation of power mag- netics of the pulse modulated parallel-inverter should be eliminated through active means. See Appendix C. (3) Source EMI Control without High Resonant Peaking. Due to the audio- frequency line disturbance (i.e., 2.8V rms), the resonant peaking of the input filter must be controlled to prevent (A) the regulation limits of the power processors from being exceeded due to low voltage resonant valleys, and (B) the filter and the converter components from being over-stressed due to peak resonance. The filter must be designed with a large damping factor, yet without a significant efficiency penalty. The two-stage input filter which represents such a design shall be used. The optimum filter design shall be enhanced by an essentially constant switching frequency independent of input line voltage at full-load operation. See Appendix D for detailed filter design. (4) Fool-proof Design. The converter must be designed to protect itself against a polarity reversal of the input line and a shorted or open converter output. 23 6.2 Control Circuit Design Guidelines (1) Commonality of Regulation Control-Signal Functions. Adoption ofthe standardized ACSP to all three converters shall lead to the commonality in per- forming the basic analog to digital control-signal functions. (2) Commonality of Control Circuits. In addition to the ASDTIC con- trol elements in the voltage and current regulators, commonality should be achieved for all the interface and peripheral circuits. The realization of this design goal shall be achieved by the design of a novel Digital Control Signal Processor (DCSP).adaptable to all converters. The DCSP shall accommo- date all control signal requirements including (A) interface with the digital signals from ASDTIC control elements, (B) provisions for duty-cycle control with either a constant on time, a constant off time, a line-dependent variable on time, or a constant frequency, (C) processing of the peak current protection of the power switch, (D) response to on/off command and enforcing an orderly converter starting, and (E) synchronization to an external clock frequency, if needed. (3) Application of Digital Control Logic. The very nature of pulse modulation control in switching regulators has paced the present trend of increasingly incorporating more digital functions in regulator and control circuits. Realizing that noise immunity is the key to reliable digital IC application in switching regulators, the High Threshold Logic (HTL) family of IC's shall be used in the design of the DCSP. It has a high input thres- hold, a large logic swing, and a relatively long propagation delay (100 nano- seconds). These characteristics make the HTL most attractive for use where electrical noise rejection is an important consideration, as well as for applications where interfacing with various discrete components is required. In addition, the following two guidelines were imposed on the digital control circuits: (A) all low-level control signals shall be dc coupled, with no ac or capacitive coupling for digital pulses; thus minimizing noise- generated false triggering, and (B) controlled time intervals wherever possible whall be mechanized using passive parts instead of regenerative one-shots to minimize noise susceptibility. 24 (4) Meeting Ripple Requirement during Dynamic Operations. To accommodate critical instrumentation and equipment loads aboard the space- craft, it is desirable to limit the converter output voltage excursion to within the ripple specification limits during dynamic input line voltage and load changes This design goal of containing the converter transient response within the limits of the ripple specification shall be achieved through the integrated design of the power and control circuits. 6.3 Brassboard Converter Package Design Guidelines (1) Division of Power and Control Circuit Modules. The power and con- trol circuits shall be separated to facilitate the demonstration of control circuit commonality among different converters. Furthermore, this separation shall isolate from the low-level control-circuit boards interference-prone power components and leads carrying high switching currents. (2) Division of Control Circuit Board into Submodules. To further standardization and to enhance maintainability, interchangeability,.and functional block identification, the control circuit shall be divided into submodules of control and protection functions. (3) Separation of High Voltage (HV) and Low Voltage (LV) Circuits. The circuit design should enable a simple division between HV and LV circuits to aid in the packaging of components. Sufficient separation of HV and LV circuits must be established to ensure reliable converter operation. To ensure personnel safety, HV components and terminals shall be totally enclosed. (4) Provision of Test Points for Control Signal Tracing. Since one of the program objectives is to introduce to design engineers the ASDTIC control system concept, selected points which permit observation of control signal flow shall be made available through a test connector. The test points shall be protected against external shorts. 25 7. CONVERTER SPECIFICATIONS AND BLOCK DIAGRAMS The program provided for the demonstration of standardized control on three types of dc to dc converters. The three most commonly used dc to dc converter configurations, shown in Figure 6, were selected for demonstrating the applicability of the ASDTIC control and of the newly developed interface and peripheral circuits: (1) the buck-boost converter, (2) the series switching buck-regulator, and (3) the pulse modulated parallel-inverter. The buck-boost converter is usually used for low part count, high efficiency applications. This circuit can achieve voltage transformation with one power switch, and by duty cycle control of the same power switch, output regulation control is also achieved. The buck-boost converter has added advantages in high output voltage applications, as the number of secondary turns in the step-up magnetics can be reduced through the use of power switch on to off time ratios greater than one. The series switching buck-regulator is the highest efficiency, lowest part count, lightest dc to dc converter. It is used where there are no input to output isolation requirements and where the single output voltage is lower than the lowest input voltage. It is also used as a pre-regulator to square wave parallel inverters where efficiency is less critical or for converter applications having multiple output voltages with wide load variations. The pulse modulated parallel inverter is used for high efficiency multiple output applications. Power inversion and requlation is accomplished in the same power stage as in the switchina-buck regulator, however, there are two power switches required, operating alternatively to effect voltage trans- formation. On the other hand, the separate LC filters in each output provide a degree of load isolation. 7.1 Converter Specifications The equipment specifications for the three dc to dc converters are summarized in Table 1. Test data showing compliance by the deliverable converter units with these requirements are provided in Section 10. 26 o(A) Buck-Boost Converter E 1 Q 0-1 (B) Series-Switching Buck Regulator QI . E Q2 (C) Pulse-Modulated Parallel Inverter Converter Figure 6. Power Configurations of the Three Demonstration Converter Models 27 Table 1. SUMMARY OF DC TO DC CONVERTER SPECIFICATIONS BUCK BOOST SERIES SWITCHING PULSE MODULATED PERFORMANCE PARAMETERS CONVERTER BUCK-REGULATOR PARALLEL-INVERTER REQUIREMENT OBJECTIVE Audio Susceptibility Test 2.8V RMS 2.8V RMS 2.8V RMS Demonstrate ASDTIC line rejection Source Current Ripple MIL-STD-461 (N3) MIL-STD-461 (N3) MIL-STD-461 (N3) Typical Space Requirement Reverse Input Protection yes yes yes Fool-proof Temperature Range -25'C to 850C -250C to 850C -250 C to 850C Abnormal space environment Input Voltage Range 20 to 40V 24 to 40V 24 to 40V Demonstrate wide input voltage range Output Power Rating 42W 40W 60W Typical equipment converter Full-Load Efficiency 90% 92% 85% Efficient Power Circuit Design Input/Output Isolation 10 Meg-ohm none 10 Meg-ohm Isolation Feature Package Weight 1.OKg 0.75Kg 2.5Kg Brassboard packaging larger and heavier than flight equip- ment to facilitate control-cir- cuit demonstration. Current Reauiatnr Adjustment 10% to 100% FL 10% to 100% FL none Sinnle loop current regulator Kegulation +_% +5% for overload protection. Output Load Voltage 28V 20V lOOOV, +15V, +5V Demonstrate buck-boost buck, and multiple outputs Output Voltage Regulator +0.2% +0.2% (Sense + +0.2%,+5%, +8% Precision Voltage Regulator IKV) for a single high voltage (Sense + +2%, +3%, +6% Good overall regulation dd/dt) -- for multiple outputs Output Load Current O.15A to 1.5A 0.2A to 2A lOOOV + 0.03A to 0.04A, Large load variation +15V - 0.25A to 0.5A, +5V - 0.5A to IA P-P Output Voltage Ripple 1% 1% 0.5%, 1%, 1% Typical for space applications 7.2 Converter Block Diagram Utilizing the guidelines presented in Section 6, a common block dia- gram, shown in Figure 7, was conceived for all three converters shown in Figure 6. The broad lines represent the flow of power from input to output, proceeding from left to right. The division between the power circuitry and the control circuitry is also shown. Before entering the description of each functional block, the fol- lowing clarifications of Figure 7 are made: (1) Since the parallel in- verter employs two power switches Ql and Q2 rather than a single switch Q as each of the other two converters, dual sets of peak-current sensors, energy-recovery networks, and proportional current drives are required, (2) The blocks enclosed by dotted lines are applicable only partially to the three converters as required, (3) While only a single output is shown in Figure 7, the pulse modulated parallel inverter actually supplies four output-load voltages listed in Table 1, and (4) A d0/dt sensor sensing the rate of flux change in the inverter transformer is incorporated in the parallel inverter as an alternate means of load voltage control in addition to sensing and regulating the lKV output, thus achieving no precise reg- ulation for any specific output, but a better across-the-board regulation for all four outputs. With these points clarified, the commonality of all three converters, based on an identical functional block diagram, becomes evident. Detailed functions performed by converter power and control blocks are presented in Tables 2 and 3, respectively. The design of these functions was guided by the groundrules prescribed in Section 6. In this program, one breadboard and two brassboards were designed, fabricated, and tested for each of the three aforementioned converters. 29 Ei REVERSE INPUT PEAK ENERGY Q Eo VOLTAGE I I CURRENT -- RECOVERY 0 FILTER PROTECTION SENSOR NETWORK ON, OFF BASIC POWER CIRCUIT PROPORTIONAL CONFIGURATION POWER BASE CURRENT CIRCUIT DRIVE (i.e., Figure 6A, B, or C) CONTROL POWER MAGNETICS i CIRCUIT I SATURATION I dIdtCIRCUIT SERIES SENSOR SENSOR REGULATOR (For Fig. 6 C only) I I Fig.6C only) ICONTROL . SIGNAL PROCESSOR < ANALOG LOOP IR(DCSP) CONTROL CIRCUIT I ANALOG L INPUTIOUTPUT SIGNALSISOLATION PROCESSOR LOOP II (For Fig. 6A, C only) (ACSP)ONIOFF , COMMAND CURRENT REGULATOR, OVERLOAD PROTECTION Figure 7. A Common Block Diagram For All Three Converters Table 2. SUMMARY OF POWER-CIRCUIT FUNCTIONS POWER CIRCUIT FUNCTIONAL DESCRIPTION OF POWER CIRCUIT FUNCTIONS BLOCKS REVERSE PROTECTION AGAINST INADVERTENT APPLICATION OF A REVERSED POLARITY INPUT INPUT TO THE CONVERTER. PROTECTION TO ATTENUATE THE ALTERNATING CURRENT COMPONENT GENERATED BY THE INPUT CONVERTER SWITCHING SO THAT THE CURRENT REFLECTED BACK INTO THE FILTER SOURCE SHALL MEET THE DESIGN GOAL, AND TO PREVENT THE SOURCE-VOL- TAGE TRANSIENTS FROM ADVERSELY AFFECTING THE CONVERTER OPERATION. OVER THE NORMAL STEADY-STATE OPERATION, THE PEAK CURRENT SENSOR REMAINS INEFFECTIVE. HOWEVER, IT DETECTS ANY TRANSIENT POWER- SWITCH CURRENT GREATER THAN A PRE-SET VALUE, AND PROVIDES AN IN- PUT TO THE DCSP TO EFFECT AN IMMEDIATE TURN-OFF OF THE POWER SWITCH. FOLLOWING A CONTROLLED OFF TIME, THE POWER SWITCH IS PEAK TURNED ON AGAIN. IF THE CAUSE FOR THE EXCESSIVE PEAK CURRENT IS CURRENT NO LONGER PRESENT, THE PEAK-CURRENT SENSOR WILL AGAIN BECOME IN- SENSOR EFFECTIVE. SINCE THE CURRENT IN OTHER POWER COMPONENTS IS INTIM- ATELY RELATED TO THE INSTANTANEOUS LEVEL OF THE POWER-SWITCH CUR- RENT, THE PEAK-CURRENT SENSOR ESSENTIALLY CONTROLS THE ELECTRICAL STRESSES OF ALL POWER COMPONENTS DURING ANY LINE, LOAD, AND CIR- CUIT TRANSIENT INCLUDING CONVERTER STARTING AND SUDDEN OUTPUT FAULT. EXISTING CONVERTERS OFTEN FORSAKE THIS FUNCTIONAL BLOCK, AND RELY ON GENEROUS CURRENT DERATING OF THE POWER SWITCH AND OTHER ASSOCI- ATED POWER COMPONENTS TO MAINTAIN RELIABLE CONVERTER OPERATION. SUCH A PRACTICE NOT ONLY PLACES THE CONVERTER AT THE MERCY OF UN- CONTROLLED TRANSIENT CURRENTS, BUT IT WILL BECOME INEVITABLY IM- PRACTICAL IN VIEW OF THE FORTHCOMING HIGHER POWER RATING OF FUTURE CONVERTERS. IT REDUCES THE SWITCHING LOSS IN THE POWER TRANSISTOR SWITCH. BY ENERGY PROCESSING THIS OTHERWISE LOST ENERGY AND FEEDING IT BACK TO THE RECOVERY INPUT FILTER, CONTROL OF TRANSISTOR PEAK-POWER DISSIPATION AND NETWORK IMPROVEMENT OF CONVERTER EFFICIENCY ARE SIMULTANEOUSLY ACHIEVED. PROPOR- IN ACCORDANCE WITH THE SIGNAL OBTAINED FROM THE DCSP, IT PROVIDES TIONAL A PROPORTIONAL BASE-COLLECTOR CURRENT DRIVE FOR THE POWER TRANSIS- BASE TOR SWITCH. ADVANTAGES OFFERED BY THE CURRENT DRIVE INCLUDE (1) CURRENT OPTIMUM BASE LOSS WITH WIDE LINE AND LOAD VARIATIONS, (2) SHORT DRIVE TRANSISTOR STORAGE TIME AT LIGHT LOAD, AND (3) IMPROVED RELIABILITY BASIC POWER MODULATION/VOLTAGE TRANSFORMATION (SINGLE OR MULTIPLE OUT- POWER PUT FILTERING, POWER-CIRCUIT INPUT/OUTPUT ISOLATION FOR BUCK-BOOST CIRCUIT AND PARALLEL-INVERTER CONVERTERS). CONFIGUR- ATION 31 Table 3. SUMMARY OF CONTROL-CIRCUIT FUNCTIONS CONTROL- CIRCUIT FUNCTIONAL DESCRIPTION OF CONTROL CIRCUIT FUNCTION BLOCKS ANALOG IT UTILIZES TWO-LOOP SENSING, DESCRIBED IN SECTION 3. LOOP I SENSES CONTROL THE AC VOLTAGE ACROSS THE ENERGY-STORAGE INDUCTOR. LOOP II SENSES SIGNAL THE CONVERTER DC OUTPUT VOLTAGE. WORKING IN UNISON WITH A THRESHOLD PROCESSOR DETECTOR, THE ACSP PROVIDES A DIGITAL OUTPUT SIGNAL TO EFFECT POWER- (ACSP) SWITCH DUTY CYCLE CONTROL FOR PRECISION REGULATION OF THE CONVERTER OUTPUT VOLTAGE. CONTROL BY NECESSITY, THE ACSP, THROUGH THE VOLTAGE DIVIDER AND INTEGRATING CIRCUIT ERROR AMPLIFIER, IS OHMICALLY COUPLED TO THE CONVERTER OUTPUT. THE INPUT/ DCSP PROCESSING THE ACSP DIGITAL OUTPUT, HOWEVER, MUST BE COUPLED TO OUTPUT THE CONVERTER INPUT SO AS TO REMAIN OPERATIONAL EVFN WHEN THE CON- ISOLATION VERTER OUTPUT IS SHORT CIRCUITED. IT IS FOR THIS REASON THAT THE CONTROL CIRCUIT INPUT/OUTPUT ISOLATION BLOCK IS NEEDED BETWEEN THE ACSP AND THE DCSP FOR THE BUCK-BOOST AND THE PARALLEL-INVERTER CON- VERTER, WHERE THE INPUT AND OUTPUT POWER CIRCUITS ARE ALSO ISOLATED. THE DCSP IS THE NERVE CENTER OF THE CONTROL SYSTEM,,AS IT MUST DIGITAL PROCESS ALL INCOMING SIGNALS AND TRANSMIT THE CORRECT OUTPUT SIGNAL CONTROL TO OPERATE THE POWER SWITCH. THE SIGNALS IT RECEIVES ARE FROM (1) SIGNAL THE ACSP AND THE CURRENT REGULATORS, (2) PEAK-CURRENT SENSOR, (3) PROCESSOR ON/OFF COMMAND, AND (4)EXTERNAL FREQUENCY SYNCHRONIZATION, IF NEEDED. (DCSP) IN THE CONTROL CIRCUIT MECHANIZATION, THE DCSP ALSO DETERMINES(1) THE CONDUCTION TIME OF THE POWER SWITCH AS A FUNCTION OF THE CONVERTER INPUT VOLTAGE, AND (2) A MINIMUM NONCONDUCTION OR OFF TIME FOLLOWING TERMINATION OF EACH CONDUCTION INTERVAL WHEN THE PEAK- CURRENT SENSOR IS EFFECTIVE. THE ACSP OR CURRENT REGULATOR ONLY OVERRIDES THE MINIMUM OFF TIME, AND LENGTHENS THE OFF TIME TO THE LEVEL REQUIRED FOR REGULATION. DURING THE CONVERTER STARTUP AND THE CURRENT-REGULATING OR OVERLOAD MODE, THE SERIES REGULATOR RECEIVES THE OONVERTER INPUT AND PROVIDES A REGULATED DC VOLTAGE FOR THE DCSP, THE CURRENT REGULATOR, THE SERIES PROPORTIONAL BASE CURRENT DRIVE, THE PEAK CURRENT SENSOR, AND THE REGULATOR INPUT HALF OF THE INPUT/OUTPUT ISOLATION. HOWEVER, DURING THE NORMAL OPERATION WHEN THE RATED VOLTAGE IS MAINTAINED AT THE CONVER- TER OUTPUT, THE SERIES REGULATOR IS CONTROLLED TO OPERATE IN ITS "OFF" STATE BY THE APPLICATION AT ITS OUTPUT TERMINALS A VOLTAGE HIGHER THAN ITS REFERENCE LEVEL. SUCH AN APPLIED VOLTAGE IS READILY OBTAINED THROUGH A RECTIFIER-FILTER IN CONJUNCTION WITH A WINDING ON THE POWER MAGNETICS OF EACH CONVERTER. BY SO DOtIG, THE POWER REQUIRED BY THE VARIOUS CONTROL SYSTEM BLOCKS DURING NORMAL CON- VERTER OPERATIONS IS DERIVED FROM THE SWITCHING CONVERTER RATHER THAN THE SERIES REGULATOR, THUS SIGNIFICANTLY IMPROVING CONVERTER EFFICIENCY. ITS FUNCTIONS ARE: (1) TO PROVIDE AN ADJUSTABLE REGULATED CURRENT AS CURRENT REQUIRED, AND (2) TO ENHANCE THE PROTECTION AGAINST OVERCURRENT, REGULATOR WHICH MAY BE CAUSED, FOR EXAMPLE, BY A SUSTAINED SHORT CIRCUIT AT THE CONVERTER OUTPUT. THE SPECIAL POWER TRANSFORMER CONFIGURATION USED IN THE PARALLEL- POWER INVERTER CONVERTER EMPLOYS TWO UNCUT SATURABLE CORES. BY LETTING MAGNETICS ONE CORE SATURATE BEFORE THE OTHER, AN ADVANCE SIGNAL IS GENERATED SATURATION WITH A CONTROLLED LEAD TIME FOR INITIATING THE TURN-OFF OF THE CON-ENSOR DUCTING TRANSISTOR. THROUGH SUCH A MECHANIZATION, THE IMPENDING CORE SATURATION IS ANTICIPATED, AND THE POWER SWITCH IS TURNED OFF SUFFICIENTLY IN ADVANCE TO ELIMINATE THE NORMALLY-HIGH SATURATION CURRENT. 32 8. POWER AND CONTROL CIRCUIT DESCRIPTIONS In section 7.2 a common functional block diagram was illustrated for all three demonstration-model dc to dc converters. In this section, circuit design and operation of each functional block will be described. The converter schematics corresponding to the three power configurations of Figure 6 are given in Figures 8, 9, and 10. Descriptions are pre- sented for all power circuits and control circuits in terms of these schematic diagrams. 8.1 Converter Schematics The dividing lines in Figures 8, 9, and 10, similar to the division shown in the aforementioned block diagram, illustrate the division of components in the breadboard and brassboard models between power circuit assemblies and control circuit modules. The pertinent electrical parameters of power-,and control-circuit parts in each functional block for allthree converters are identified in Appendix E. 8.2 Power-Circuit Description Basic Power Stage Configurations The basic power-stage configurations for the three converters are described in Tables 4, 5, and 6and Figures 11, 12, and 13. The presentation includes operations, waveforms, design equations and criteria used in designing the basic power stages. Other Power Circuit Blocks To facilitate a smooth flow of concise technical information in the main text of this report, the very detailed circuit descriptions and design criteria of power circuits associated with all three converters are being reserved in its separate entirety. Readers who are particularly interested in specific design and operation details of the converter power circuits are hereby referred to Appendix F. 8.3 Control-Circuit Description Similarly, circuit descriptions and design criteria of control- circuit functional blocks for all three converters are presented in Appendix G. 33 Jl FI LI L2 5. T I 6 L5 CR9 T3 J2 2 0-40 ___ _____ '6 28V SCRIO CRI2 C8.5A MAX ADI - CRI 1 CR12 C8__2C13 J3-2 OMMAND 2 R7 RETON/OFF CR5 9 TU 7>C4 T7 2 S 4 14 CUR. R4 LI M CR C ADJ _. ADJR 3 Q 2 C R7 Q 3 202 12 CR6SRE 5 QI 3 TEST POINTS L4 T J3 CRI C2 R2 ---- I OUPT RET C. . . t+ R 7- 2 SEC V RI VRI 0R RET-- 3 INP RET. INPUT J3 THRESHOLDRETURN 5 R9 E I4 5 INTEGRATOR R5 5OUPT GI 1" ------ H - 6 PULSE GEN A l POWER - .. -( ... I6 I I 3 1CR72 C73C3 1 2 R33 R78 C31 4 U31 C32 :R53 R54 C 71 R32 R341 12 13 6 8 64 3 40 5 9 U52 VR51 40O + SERIES REG _0A DTIC CUR. REG & ( - -41 C74 PEAK CURRENT - JI-6 PROTECTION J8 R71 R R74 -7ROTE-,. JI-9 39 77\30 R72 38 + 37 + R73 - + + 5 62733 34 35 42 -+ 10 3 3 711 C U71 R 7 C 5 U92 5 U92 U93 U93 R91 U U 9 ASDTIC VOLTAGE REGULATOR 2C91 1 I4 1 1431 9 SERIES INDUCTOR BULK-BOOST POWER PROCESSOR 13 2 )12 1 CRIOI 7 _ 7 7 RIO5 - U92 U93 U93 R RIO2 s 1 U91 R9O Ul 2 1 4 2 102 C92 3 2 I U-- lR01 C RI04 U1O3 A2 CONTROL PULSE GENERATOR INPUT/OUTPUT ISOLATION Figure 8. Schematic Diagrn of the Buck-Boost Converter 4 FOU)OT IRAME OOUT FRAM7, J; FI LI L2 TI L5 CR9 J29. 6 9. 42040 T.5A MAX V DC I2 CR2 Ir cI +;CR2 C! CRI2 CS C13 7 J3-2 81 OUTPUT 2 11 1 RETURN C4 T2 c C1 02 CR7 IIMJa~- R4 I 02 C 00,1 CRs5 7 0 TEST POINTSJ3 L4 CR I OUPT RET.F-L41 919 62 I3 R7 < 2SEC V I0 i RET.--< 3INPRET.JVRI iRS THRESHOLD _4 4 DET OUPT u 4 R9 INTEGRATOR ____ - P GEOUPT ___G -' PULSE GEN ----- ------ _272 R 5 31 c U2%,C RC56 9 C 3I~ I c2 0 r -15 P34 U9 2 3 U .I P E A K C U R R E N T U 1 1 TROL 77 I JI-7-~i R72 P73 R i gre- a-I Pceai DP oo74 t e N32 I.9 G 13 3b I 5 u92 'U92 'U93) U93 C'>_ _iiI I, . - ASDTIC VOLTAGE R GULATOR IL3 - -4 -2--- CR101 1 SERIES INDUCTOR BULK-BOOST POWER PROCESSOR IA 7 10 __ _ 105 092 u93 U93 -,- 410 0102U9, A2 cU ROLF- I ACNIRO - ~j ~~7 P10 5 I ................. I.K AULSE OENIEPATOP 1P0/OITPUT ISOLTION Figure 8. SchematiC Diacram of the Burk-Boost Converter 1AM L3 CR5 JI FI LI L2 5 TI GT Q2 T1- 2 q 00 T2 J2 0V 24-40 ' .I . 4As 7j 4 M6AX COMMAND 4 I J2 3 P ON/OF F AS T4. R7' I SF- CS5 C C7 CR12 OUTPUT R 1--- A DE OUPT IL+ + < 0 UPT RETC.3 .. .9 3 1,U1 CG TOR INPUT ~I J A D C R 133 - T E S T P O IN T S -T TU 1 RETURN OUTPUT 2J 3- R 9 J3 -3 3 R E R AT -S I T57C - - -- - G & c A- -8- J R33 R55 CRU J9 C3 U31 3 72 o o ', I3 R 95 C2 C7 76 .92 U9Z U93 U93 PULSE GENERATOR A2 CONTROL Figure 9. Schematic Diagram of the Series Switching Buck Regulator Lrn c II I i- (.h i :I El -i.. ,, i~LL~ " " .. /- ... 'I IT Tl I 1 P 1J '" I: t' fl'.. . .. "4 . . ... . .-. "1 _ _ ;,r 1 "_ _ ......... . _-- ... .. ... ~~~~" c !u ] 4- C., ., v~~~u J-4a I --- ,,."... L;! ,? _ _ _ _ ___-I _ ,'iI!/ "- ::--- . .... "' . . --_. .. . ... __ ; .. ." .. . . . 4~ m - IT T1 -L _ UU L i ,=, t ~ ~ ~ ~ ~ ~ ~ ~ ~ ."" -- ::""'-- ! "'i II / I_ r p v I -- "-1 '1 I I .- ,- o ,- F u c I J J . D- 7 59 R UE Wa F 1g ur e 10. SchemtIc Dkigrarn of the Pulse Modulated Paral lel -Inverter Converter Table 4. BASIC BUCK BOOST CONFIGURATION (1) CIRCUIT AND WAVEFORMS i 2 L5 D CR In Figure ll(A), the energy-storage inductor 'c2 CO utilizes a core which has a fairly linear flux vs MMF * CRI Scharacteristic. Energy is derived from the power source C2 N N2 1 8toCI RL (in this case through the input filter), and stored * inductively in the inductor during on-time interval T when power transistor Q2 is conducting. When it is n turned off, a current flow through the inductor secon- daries must occur, since the MMF of the core cannot (A) change instantaneously. Thus the energy previously IQ t t stored in the primary inductance during Tn is delivered 2 from the secondary winding during the off half cycle, t Tfas output energy. Through fast recovery diodes CR9 ln 1 t and CRIO, the energy is received by the load and filter capacitors C8 through C13. Notice that the energy is tD D N tdelivered to the output in the form of a series of uni- Sdirectional current pulses, allowing the output filter to be merely capacitors. 'C2 C2 t Jt Depending on the line and load conditions, the operating waveforms for a given design can have either a non-zero MMF in the inductor at heavy load, or a zero MMF Ct C during a portion of the power switch off time in each cycle at light load. VQVQ (C). These two conditions are shown in Figures ll(B) and VD t VD (B) N2Ei (C) -(E + )o N Figure 11. Buck Boost Converter Configuration and Waveform. oTable 4. BASIC BUCK BOOST CONVERTER CONFIGURATION (CONT'D) (2) DESIGN CRITERIA Based on relationships for volt-second balance on the With an input voltage variation between 20V to 40V and a inductor and energy balance for the converter, time in- regulated output voltage at 28V, a unity turns ratio for Nl tervals t1 and t2 are derived in terms of Tn , input E., and N2 becomes attractive for two reasons: (1) Such a turns output Eo, and load resistance RL, where ratio will cause a duty cycle that does not approach zero or unity, thus relieving the switching characteristic require- EiT n N2 ments of semiconductors and leaving ample time to reset t = E N various magnetics; (2) Such a turns ratio facilitates the o NE use of bifilar windings for l and N2. With N2/NI = 1, E = eE2RLT - 2L E (E + 2 N 28V, e = 0.9, El = 20V, EiT n = 560 x - 6 vs, and Rk = 60 ohmsI Ln p o Nl (i.e., about one-third of full load), inductance L is calcula- t2 2 Tn ted to be 220UH. P 2L E ° Using the same notation, the peak flux density in the core, Here, e is the efficiency, and L is the primary inductance Bp, is of the converter. Notice that a critical R = R exists, below which t2.becomes negative, i.e., physical y unrealiza- P Lp N2E E.T ble. This resistance value can be predicted by letting t2 B = o (1 + + ' A = core area be zero, and solving for RL, where o Equations prescribing a minimum weight inductor design are E N2 given in Appendix ,which are also applicable for inductor 2L Eo ( + -) design of other converters. RL = Rk = eE.T To reduce the core loss, a ferrite toroid with cut gaps alongi n its diameter was selected to achieve the desired permeability. The period of T for each steady-state cycle is: The converter efficiency improvement as a result of changing to the ferrite core was calculated to be about one percent. EiN 2T = T + t = T (1 + )--) RL < R For a given inductor and a specified EiT , the steady-state n n EN 1 -- k power rating of the transistor and the diode are readily deter- mined from the worst-case voltage and current over the range eRL(EiTn ) e(EiTn ) of line and load variations. Other selection criteria include T = Tn + tI + t _2 2L P Rk < RL the current gains, the conduction voltage drop, the switching n 1 2 2L E 2 2L o characteristic and its effect on control circuit noise suscep- P o tibility, the storage time, and the secondary breakdown sus- where P = E /RL is the converter output power. ceptibility.0 L From a weight viewpoint only, a C-L-C filter is more attractive In this design, T k 40js for RL - R . than a capacitor filter. However, the capacitor filter is Tradeoff studies were undertaken to identify the optimum superior with respect to its power loss and its output imped- power circuit design. The study results indicated that, with ance, and is selected for the design. AC capacitors with neg- the specified line and load ranges, the design giving a zero ligible ESR's, such as the polycarbonate type, were considered t2 at heavy load and a non-zero t2 at light load, would pro- but not chosen, due to their excessive size and weight. Six vide the highest efficiency and minimum weight. To carry out tantalum-foil capacitors in parallel, with 1001F each, are then this design philosophy, the threshold between zero and non- chosen to meet the 1% peak-to-peak output ripple requirement zero t_ is set to occur at a converter input voltage of 20V at the cold environment (-250 C) when the ESR of the capacitor and an gutput corresponding to one-third of the full load. is the highest. Table 5. BASIC SERIES SWITCHING BUCK REGULATOR CONFIGURATION (I) CIRCUIT AND WAVEFORMS E Q -VQ- L4 E i i 2 E In Figure 12(A), transistor Q2 is controlled by iC2 iCO the ASDTIC module to turn on and off cyclically CRI2 RL for respective time intervals T and T . During C5toC7 Tn, CR12 is reverse biased, and voltage Ei is ap- D plied to the output filter. During Tf, CR12 con- (A) ducts to maintain the MMF continuity in L4, and an essentially zero voltage is applied to the filter. After averaging by the filter, a dc out- iQ put voltage Eo is obtained. 0 Oki _Tn* 1 1 t t 'C2 'iC2 CO 'ICO V VQ E-E (B) (C) Figure 12 Series Switching Regulator Configuration and Waveform 0Table 5. BASIC SERIES SWITCHING BUCK REGULATOR CONFIGURATION (CONT'D) (2) DESIGN CRITERIA In the subject converter, the control circuit is implemented Similar to the buck-boost converter, the approach for in such a way that time interval Tn is inversely proportional t2 = 0 at heavy load and t2 > 0 at light load yields optimum to input voltage Ei, or, efficiency and weight. The threshold between zero and non- T =Constant zero t2 is designed to occur at an input of 32V and an out-n E. put corresponding to one-third of the fu 1 load. With Eo Based on relationships for volt-second balance on the induc- 20V, e = 0.92, E = 32V, EkT = 600 X 10o VS, and Rk = tor and energy balance for the converter, time intervals t 250 ohms, inductance L is caculated to be approximately and t2 are derived in terms of Tn, Ei, Eo, and RL, where 250 E.-E The peak-flux density in the core is: t1 E T LP (E.-E )T O B O I on dR 2 (E-E)2L 2 p NAE 2NA dRE -Eo)-2L EiE o ot - T2 3 n2L E where N is the number of turns on the inductor, and A is the cross sectional area of the core. Using the magnetics design Here, e is the efficiency, and L is the filter inductance, equations presented in Appendix 8, the optimum permeability is Notice that a critical R = Rk esists, below which t2 becomes determined to be 125 gauss/oersted. Preliminary weight and negative, i.e., physical y unrelizable. This resistance efficiency estimate shows that the required efficiency of value can be predicted by letting t2 be zero, and solving 92% can be achieved without special ferrite core design. for RL, where Consequently, a molypermalloy powder core is used for the 2LE 2 inductor. RL = Rk eEiT (Ei-E ) The selection criteria for Q2 and CR12 are similar to those presented for the buck-boost converter. From equations representing Tn, tl, and t2, the period T of a steady-state cycle is Three tantalum foil capacitors, each a 100PF, are used to E.T meet the 1% ripple requirement at -250 C when the ESR of each T = Tn + tl = E RL < Rk capacitor is the highest. o E. e(- - I)(E T )2E n T = Tn + t + t2 = 2LP , R < R n 1 2 2LP k 0 where P = E 2 /RL is the converter output power. In this design, T 30 Ps for RL < Rk _L k Table 6. BASIC PARALLEL-INVERTER CONVERTER CONFIGURATION (1) CIRCUIT AND WAVEFORM TI in pulsewidth modulation (PWM) converter shown in Figure 13, each of theSDI two switches, SI or S2, is controlled to turn on and off cyclically; con-I = duction of both SI and S2 are mutually-exclusive events. The L C filterN 0 of each output receives an input voltage corresponding to (N IN E 0AA T N during Tn, and receives an essentially zero voltage during T. This e C voltage pulse train is averaged by the output filter to yield the requiredEE 0 Coutput voltage.S2 _ B The utility of high-power parallel inverter has been hampered by high- S2 02 stress conditions caused by the saturation of the power transformer. Saturation is either necessary to turn off the conducting switch, [29] or it is inevitable due to asymmetry between the two inverter halves. The asymmetry cyclically impresses a differential volt-second increment to the core, resulting in its ultimate saturation at one end of its BH loop. Even% L when a saturation sensor is used, the inability of the transistor switch2 to turn off immediately after detection of saturation by the sensor (dueto signal delay and the transistor storage time) generally results in a very high saturation current before the eventual interruption. This high(A) current causes heavy electrical stresses on transistor switches, which results in lower converter efficiency and reliability. Such losses es- tablish an urgent need for a method to anticipate the impending coreSl saturation. The anticipation initiates the turn-off of the power switch sufficiently in advance of saturation, so that by the time the switch isS T for Switch Sl opened, appreciable saturation current is yet to materialize. A published two-core transformer configuration [30] seemed applicable forfulfilling such a need. The design was originally intended for a free-running parallel-inverter. Extending the same technique to a PWH parallel-inverter converter was investigated and experimentally demonstrated by first designing and operating a low power, low voltage PWM parallel inverter usingSthe two-torn configuration. Successful completion of this task led to thehigh power, high voltage design meeting all the requirements for the variousSloads specified in this contract. The transformer configuration employs two identical, uncut saturable cores. By letting one core saturate before the other, an advance signalis generated with a controlled lead time for initiating the turn-off of the conducting transistor. Through such a mechanism, a complete pre-vention of saturation-current spike is achieved. 0 (B) Figure 13. Parallel-inverter Converter Configuration and Waveform Table 6. BASIC PARALLEL-INVERTER CONVERTER CONFIGURATION (CONT'D) (2) DESIGN CRITERIA e = Ee I (N + NC The transformer contains two identical cores TI and eRA eRB 2NA T2, push-pull primary windings NA and NB, control winding NC, and two flux-sensing windings ND and NE. Windings NA, Notice that a voltage of this amplitude exists whenever NB, and NC are common to both cores, while winding ND is core TI is saturated and core T2 is not. The voltage on Tl only, and NE is on T2 only. The circuit loop con- becomes an excellent anticipation signal for the pending tains NC, ND, and NE is closed by resistors RA and RB. saturation of T2. The proper design, therefore, is to Generally, NA=NB, ND=NE, and RA=RB. utilize the leading edge of this voltage signal to initiate the turn-off of Switch Sl. Taking into considera- To analyze the steady-state performance of the two- tion the signal transport delay and the storage-time delay core transformer, let both core flux start ascending from of SI, this design ensures that core T2 will not saturate their respective negative-saturation flux levels. The five within these delay intervals, thereby eliminating any satu- equations governing the circuit operation, based on Sl con- ration current associated with the two-core transformer. ducting, are A detailed transformer design and discussion is presented in Appendix C.- de1 ND d -= e The inductor in each output is designed to have an MMF greater than zero during steady-state operation. The output de2 inductance Lo is therefore determined by the following con- N -d = e straint:E dt E E (T )o (Tf)max d, d 2 0 o 21 NA d- T ) = E. o min where E and I are the dc voltage and current associated with N d 2 ) the respective output. Using this equation, L for the IkV,C dt dt the +15V, the -15V, and the +5V output are designed to be 0.7H, 1.25mH, 1.25mH, and 0.53mH, respectively. -eRB + eE + eC - eD + eRA = 0 The peak flux density in the core inductor is LP ETf The last equation above can be simplified by neglecting P NAE 2NA eRA and eRB, which holds during normal converter operation o when TI and T2 are not saturated. By so doing, solutions where N is the number of turns on the inductor, A is the cross- for d&l/dt and d 2/dt can be derived as: sectional area of the inductor core, and P is the output power. It is clear that the maximum Bp occurs at the maximum d1 Ei E + NC load and the maximum line voltage when Tf is the longest. dt NA ND + NE A high voltage 15PD114K capacitor, made by Component Research, is used for CO1 across the IkV output. This de2 Ei NE - NC capacitor provides the least weight, and is experimentally2 +NC confirmed to meet the specified ripple requirement. dt NA ND NE The solid tantalum capacitors used in the other outputs are selected to meet the specified output ripple requirementsThe above two equations identify the faster d 1/dt in at the cold environment when the ESR's of the capacitors are relation to d42/dt. The positive saturation flux level of the highest. Their voltage ratings are selected to be much core TI is thus reached first, with T2 still unsaturated. higher than the respective output voltage specified. Thus, During the time interval when dl/dt = 0 and d 2/dt > 0, in case of an inadvertent open load on any output. the a large voltage is impressed across eRA and eRB. Assuming abnormally high open load voltage due to peak chaeging of RA = RB, and with dbi/dt = 0, one has: the capacitor will not cause them to fail. 9. CONVERTER FABRICATION One breadboard and two brassboard demonstration models were fabri- cated for each of the three converter types. The deliverable breadboards were built with the objective of achieving easy accessibility to all com- ponents. The brassboards were packaged similar to flight equipment brassboards with the understanding that they were not required to undergo any vibration or other environmental tests except for temperature testing. The following paragraphs describe the features and design characteristics of the brassboard prototypes: 9.1 General Mechanical Design Features The following general design features were incorporated: " Each converter has an aluminum sheet metal baseplate to which all power items are attached. * Removable cover completely encloses the converter. No parts are mounted on the cover. * The power circuit and the control circuit of each converter are separated into different subassemblies. The division facilitates the demonstration of the universal control circuits, exhibits modular capability, and isolates the control circuits from leads carrying high current at the power switching frequencies. Specific features of power-circuit fabrication include: * The power circuitry is mounted directly onto the baseplate, thus, providing a good heat sink. * Power components were placed to follow the circuit flow from input to output. * Careful consideration was given to provide short leads that conduct high-frequency current, and to separate them from those leads carrying critical control circuit signals, thus, minimizing electromagnetic interaction. 43 Specific features of control-circuit fabrication include: * Modularization concepts were used in the layout of the control- circuit boards. The series regulator, the standardized DCSP, the input/output isolation, the ASDTIC voltage regulator, and the current regulator, are located on separate printed circuit boards. These modules are mounted on an epoxy glass base and are inter- connected by jumper wires. The modular construction aids in (1) the identification of each functional block, (2) the main- tainability of the control circuitry, and (3) the multiple use of parts common to all three units. The whole control board is secured on four standoffs that mount to the baseplate. * Test points showing critical control signal flow are brought out through a connector. Each test point is protected by a ser- ies resistor. These resistors are designated as R5 to R9 in the buck-boost converter, as R7 to RIO in the series switching buck- regulator, and as R15 to R18 in the pulse modulated parallel- inverter converter. * A copper ground plane is provided on the printed circuit board of the voltage regulator to assist heat dissipation from the micro- miniaturized ASDTIC control module. 44 9.2 Converter Outline, Interface, and Weight TABLE 7. SUMMARY OF CONVERTER SIZE, INTERFACE, AND WEIGHT Specified Overall size MaximumConverters Overall size Interface Connectors Converter Weight Maximum (Output Power) (gram) ConverterWeight (grams) Buck-boost converter 170.2x177.8x45.7 Three Cannon D, one for input power, 862.3 without cover, 1000 (output power 42W) one for output power, one for test or 20.5 g/watt points. 976.6 with cover, or 23.2 g/watt Series-switching buck 170.2x152.4x45.7 Same as above 682.5 without cover, 750 regulator (output or 17.1 g/watt power 40W) 784.5 with cover, or 19.6 g/watt Pulse-modulated 152.4x127.0x193.0 Three Cannon D, one for input power, 1629 without cover, or 2500 parallel-inverter one for low-voltage output, one 27.1 g/watt converter (output for.test points. The high-voltage 1868 with cover, or power 60W; four out- output is supplied from a high-or put voltages, of which voltage connector, which can be 31.1 g/watt one is high voltage). totally concealed during converter operation for personnel safety. 4:- 9.3 Converter Assembly and Subassembly 9.3.1 Buck-Boost Converter The various subassemblies of the mechanical structure are clearly visible in Figure 14, in which the brassboard converter is shown with the cover removed. Power components are mounted directly onto the baseplate. Also, the control board secured on four standoffs are mounted to the base- plate. The interconnection between the power board and the control board is provided by a jumper wire cable. The control board can be detached from the baseplate and folded out for easy inspection. Starting from 'the upper right corner of the printed-circuit control board and tracing clockwise, the control-circuit modules are (1) the Digital Control Signal Processor - DCSP, (2) the series regulator, (3) the ASDTIC current regulator, (4) the ASDTIC voltage regulator using the micro- miniaturized ASDTIC control module, and (5) the input/output isolation. 9.3.2 Series Switching Buck Regulator Converter The mechanical-structure assembly, shown in Figure 15, is similar to that of the buck-boost converter, with one notable exception. The "input/ output isolation" subassembly is absent, as there is no such requirement for the series-switching buck-regulator converter. 9.3.3 Parallel-Inverter Converter This converter has a different mechanical structure from the other two converters, due to the multiple outputs and the separation and isolation required for the high voltage power circuits. The configuration is shown in Figure 16, with the cover removed. An aluminum sheet metal baseplate provides the mounting surface for the mechanical structure and electronic subassemblies. Internally, there are two aluminum sheet metal trays for mounting the electronic components. The components in the input filter circuit are mounted on one of the end plates along with the input connector, shown on the left side of Figure 16. The low voltage circuit and the control board are mounted on opposite sides of the middle sheet metal tray. The sheet metal tray on the right is the mount- ing surface for the high voltage circuitry on one side and the inverter section 46 JJ, Figure 14. Buck-Boost Converter Barassboard Configuration 4- 00Figure 15. Series Switching Regulator Brassboard Configuration Figure 15. Series Switching Regulator Brassboard Configuration ~,~li,~::: ~ _:I :~:-. 4 ~a~~~~~~~~I:: I~ ::::i~:~1~ : -- ::~~ 'N.: _~ ii:::'::~ : : ::: :::o Fiur 1 . ar lll-n ererCovete Basbar Cnfguato on the other side. These aluminum trays provide (1) adequate structural support for these components, (2) low thermal resistance path for conducting heat away from the power components, and (3) adequate separation between input components, the high voltage circuitry and the control circuit. Insulated terminals are mounted on the heat sink for attachment and wiring of the power circuit components. High voltage components are carefully separated and insulated to avoid voltage breakdown. The control board is similar in concept and construction as the control board for the other two converters; it is slightly larger in size. The same considerations were given to the placement of components and separation of critical leads as were done for the other two converters. 9.4 Test Points To exhibit the critical signal flow of the ASDTIC control system, suitable test points are provided for each converter. Observed waveforms from these test points include: e Inductor voltage EL, which is the ac signal input to the integrator * Integrator output voltage E I * Threshold detector output voltage ED * Digital control signal processor (DCSP) output voltage Ep The test points are brought out to a connector, each through a series resistance for isolation purpose. Using the buck-boost converter as an example, the test points are marked in the simplified control-system block diagram shown in Figure 17. SE L o DCSP Threshold In- - Ep ED Detector E+ Figure 17. Regulator and Digital Control Signal Test Points 50 10. CONVERTER STEADY-STATE PERFORMANCE Typical steady-state performance data taken on the three types of converter brassboards over the line, load, and temperature ranges are summarized in Tables 8, 9, and 10. These tables demonstrate that the converter capabilities either meet or exceed the specification requirements. Unless otherwise specified, all test data were taken based on the following specified input voltage, output load, and temperature ranges: Converter Input Range (V) Load Range (W) Temp Range (°C) Buck-boost converter 20 to 40 4.2 to 42 (28V) -25 to 85 Pulse modulated 30 to 40 (IkV) parallel-inverter 24 to 40 3.75 to 7.5 (15V) -25 to 85 converter 3.75 to 7.5 (-15V) 2.5 to 5 (+5V) Series switching buck- 24 to 40 4.0 to 40 (28V) -25 to 85 regulator converter 51 Table 8. STEADY-STATE PERFORMANCE DATA FOR BUCK-BOOST CONVERTER Maximum Output Temp. E. (lin)DC (Al. )p-p ripple I0, E (6E )p-p ripple Switching Current Deviation (0C) (V) (A) (mA) (A) (V) (mV) Freq. from Regulator (kHz) Setting (mA) 20 2.291 12 1.473 28.029 210 27.8 5.5 0.293. 12 0.150 28.028 65 16.1 2.5 1.517 14 1.473 28.029 165 27.8 -- 0.197 25 0.150 28.028 65 10.6 -- 40 1.137 7 1.473 28.029 160 27.8 3.5 0.149 23 0.150 28.029 75 8.8 2.0 2.336 20 1.472 28.022 210 25.6 16.5 0.295 20 0.150 28.022 70 12.5 5.0 +85 30 1.534 18 1.472 28.022 180 25.6 -- 0.198 35 0.150 28.022 90 8.7 -- 40 1.151 13 1.472 28.022 170 25.6 8.0 0.151 40 0.150 28.022 90 7.3 3.5 2.284 10 1.471 28.030 240 30.0 520 0.296 20 0.150 28.029 60 16.6 4 1.513 8 1.471 28.029 200 30.0 -- -25 30 0.199 25 0.150 28.029 75 12.5 -- 40 1.139 5 1.471 28.029 190 30.0 3.5 0.151 35 0.150 28.029 80 10.0 5 Table 9. STEADY-STATE PERFORMANCE DATA FOR SERIES-SWITCHING BUCK REGULATOR Temp E. (lin)DC (AI. )Peak Ripple I EO ~ . (AEO .)P-P Ripple Switching Maximum Output-Current (ic) () (A) (mA) (A) (v) (mV) Frequency Deviation from Regulator (kHz) Setting 24 1.758 3.0 1.987 20.021 30 33 1 0.202 2.0 0.199 20.022 25 31 3 +25 32 1.341 6.0 1.987 20.021 60 31 --0.161 6.0 0.199 20.022 70 19 -- 40 1.079 6.5 1.988 20.021 80 31 1.5 0.132 13.0 0.199 20.022 100 14 3 24 1.769 2.0 1.987 20.014 30 32 30.204 1.0 0.199 20.015 25 32 4.5 +85 32 1.349 6.0 1.987 20.014 60 30 0.164 6.0 0.199 20.015 75 17 -- 40 1.094 7.0 1.987 20.014 80 30 1.5 0.135 6.5 0.199 20.014 100 13 4.5 24 1.748 3.0 1.986 20.017 40 33 2 0.200 1.0 0.201 20.017 30 28 3.5 -25 32 1.331 5.0 1.986 20.017 65 33 --0.160 3.0 0.201 20.017 80 22 -- 40 1.076 5.0 1.986 20.017 90 34 2 0.133 8.0 0.201 20.017 110 16 5 Table 10(A). STEADY STATE PERFORMANCE DATA FOR PULSE MODULATED PARALLEL-INVERTER CONVERTER (REGULATING IKV) Temp. Ein (in ) DC out Eou t (E out)P-P Ripplein in out out ouFrequency ( 0 ) (v) (A) 1 kV +15V -15V +5V I kV +15V -15V +5V I kV +15V -15V +5V (kHz) (mA) (mA) (mA) (mA) (V) (V) (V) (V) (mV) (mV) (mV) (mV) 24 2.998 41.60 511 504 1028 1000.58 15.281 15.270 5.286 700 50 50 30 22.8 2.046 31.70 256 253 530 1000.26 15.291 15.280 5.342 900 50 50 25 22.4 25 32 2.295 41.60 511 506 1034 1000.58 15.366 15.360 5.322 1200 70 70 40 21.2 1.576 31.70 259 255 525 1000.26 15.455 15.447 5.401 1050 70 70 40 24.4 40 1.828 41.60 511 508 1029 1000.57 15.276 15.262 5.293 1500 70 70 40 23.81.260 31.70 254 251 526 1000.29 15.194 15.185 5.306 1500 70 70 40 23.8 24 3.035 41.60 518 506 1039 1001.11 15.367 15.352 5.353 800 50 50 20 21.62.069 31.80 258 253 538 1001.07 15.374 15.362 5.424 750 50 50 20 23.6 2.319 41.60 515 510 1050 1001.12 15.490 15.481 5.412 1200 65 65 30 22.885 32 1.605 31.80 261 258 547 1001.08 15.591 15.571 5.513 1250 65 65 30 24.0 40 1.871 41.60 516 508 1045 1001.09 15.428 15.413 5.591 1700 75 75 40 22.21.287 31.80 257 254 541 1001.10 15.420 15.416 5.456 1600 75 75 40 22.4 24 2.960 41.50 507 500 1005 999.43 15.158 15.148 5.196 800 50 50 20 23.81.982 30.60 254 251 520 999.59 15.165 15.154 5.256 800 50 50 30 23.6 -25 32 2.259 41.50 508 500 1008 999.43 15.193 15.186 5.217 1300 70 80 35 23.2 1.524 30.60 256 251 523 999.58 15.255 15.247 5.291 1300 70 80 35 23.2 40 1.823 41.50 508 501 1010 999.42 15.200 15.186 5.227 1600 80 80 45 24.81.247 30.60 254 250 520 999.56 15.146 15.134 5.252 1600 80 80 40 24.6 TABLEIO(B). STEADY-STATE PERFORMANCE DATA FOR PULSE MODULATED PARALLEL-INVERTER CONVERTER (REGULATING d0/dt) E. (V) Temp Eo (kV +15 +5 (V) Tv) (V) 25"C 989.59 to 1005.13 15.198 to 15.310 5.266 to 5.356 24 to 40V 850C 977.20 to 989.37 14.993 to 15.202 5.258 to 5.371 -250 C 998.96 to 1013.75 15.234 to 15.342 5.241 to 5.331 Remarks: (1) +15V have identical output voltage (2) No current data are taken, for efficiency should be identical to the case where IkV is regulated. (3) The output-voltage variation represents the worst-case data under the conditions of: (a) Max. load on all outputs (b) Min. load on all outputs 10.1 Output Voltage Regulation The output-voltage regulation data for all three converters are presented, respectively, in Tables 8, 9 and 10. The regulation at minimum load, of the buck-boost converter and the series switching buck-regulator converter,was measured at open-load and at the specified 10% of full load. While the open-load test data is not shown in Tables8 and 9, it was recorded in the test report. Insignificant changes were noted when the minimum load is decreased from 10% of full load to open circuit. The regulation performance data for all three converters over the specified line, load, and temperature changes are summarized in Table II. Table 11. SUMMARY OF OUTPUT-VOLTAGE REGULATION Converters Outputs (V) Requirements (%) Measurements (%) Buck-boost 28 +0.2 *+ 0.014 Buck-regulator 20 +0.2 *+ 0.020 IkV d0/dt IkV d0/dt Regulated Regulated Regulated Regulated Pulse Modulated Parallel-Inverter 1000 +0.2 +2 +0.085 +1.83 +15 +5 +3 +1.48 +1.11 -15 +5 +3 +1.47 +1.13 +5 +8 +6 +3.16 +1.38 * Including no load. 56 10.2 Efficiency Converter efficiencies for nominal full-load operation at room temperature are summarized in Table 12. Table 12., SUMMARY OF CONVERTER EFFICIENCY AT FULL LOAD AND ROOM TEMPERATURE Converters Input Voltage Measurement Requirement (V) (%) (%) Buck-Boost 20 90.1 30 90.7 90 40 90.8 Series Switching 24 94.3 Buck-Regulator 32 92.7 92 40 92.2 Pulse Modulated 24 87.6 Parallel-Inverter 32 85.3 85 40 85.6 10.3 Output Current Regulation The current-regulator performance of the buck-boost converter and the series-switching buck-regulator converter during overload and short circuit is shown in Tables 8 and 9 as Deviation from Regulator Setting; the reg- ulator setting being adjustable from 10% to 100% of full load. In the case of the parallel-inverter converter, the overload protection causes the converter to turn off when a severe overload or a short curcuit occurs. The current regulator and limiter performances for all three converters are summarized in Table 13. 57 Table 13. SUMMARY OF OUTPUT-CURRENT REGULATION Converters Outputs (A) Requirements (%) Measurement (%) Buck-Boost 1.5A Max +5 of full load +1.23 0.15A Min +5 of full load +0.40 Pulse Modulated Four outputs None Converter turn-off when Parallel-Inverter any of the four outputs is overloaded or short- circuited. Series Switching 2.OA Max +5 +0.150 Buck-Regulator 0.2A Min +5 +0.25 0b.4 Output Voltage Ripple The worst peak-to-peak switching-frequency ripple for each converter is summarized in Table 14. Table 14. SUMMARY OF OUTPUT-VOLTAGE RIPPLE Maximum Ripple Maximum Ripple Conditions of Converters Output Allowed (mV) Measured (mV) Maximum Ripple (V) Buck-Boost 28V 280 240 Low line, heavy load, and low temperature Pulse Modulated IkV 5000 1800 Parallel- +15V 150 80 High line, light load, Inverter -15V 150 80 low temperature + 5V 50 45 High line, light load, Series-Switching 20V 200 110 low temperaturelow temperature Buck-Regulator 10.5 Source Current Ripple The design goal for the conducted interference was MIL-STD-461A (Notice 3). Over the specified line, load, and temperature range, the switching fre- quency variation for each converter was: 58 Buck-Boost: 7.3kHz to 30.0kHz Series-Switching 12.8kHz to 33.0kHz Buck-Regulator: Pulse Modulated 21.6kHz to 24.8kHz Parallel-Inverter: Within these frequency ranges, all data points for the measured source- current ripple were within the limit specified by the design goal. 10.6 Audio Susceptibility A 2.8V rms sinusoidal voltage was superimposed on the nominal DC input to test the converter's capability in rejecting the line disturbance. For each converter, the mean of the specified input voltage was selected as the DC input. The measured line rejection in "db" are shown in Fig.18, for all three converters. The data include both heavy and light load operations at room temperature. Here, the "db" is defined as audio output ac voltage output dc voltage db = 20 log 10 audio input ac voltage input dc voltage For the buck-boost converter, the significantly different rejection as a function of load is due to the different MMF status in the energy-storage inductor. In heavy-load operations, a trapezoidal current in the inductor windings during on-time Tn and off time Tf never let the inductor MMF to vanish. The average value of the trapezoidal inductor current must decrease (increase) as the line input is increased (decreased), requiring the inductor to adjust its average stored energy continuously during the audio test. In contrast, a triangular inductor current in light-load operations has a time interval of zero MMF within each steady-state cycle. This time interval makes it possible for the inductor to achieve equilibrium between its energy storage and energy discharge (i.e., a zero net incremental energy) within one cycle of converter switching despite the much slower input-voltage variation at the audio frequency. In the case of a trapezoidal current where such an interval is non-existant, the inductor energy balance can only be achieved through a cyclic migration of the minor BH loop, which can 59 -40 Attenuation, db -60 Curve (1): Buck Boost Cony., Ei=30V, E =28V, Full Load 42 W \I o -80 Curve (2): Series Switching Buck., E =30V, Eo=20V, Full Load 40W Curve (3): Parallel-Inverter Conv., Ei+32V, E° IkV, Full Load 60W -I 1 10 100 lK )OK lOOK Frequency, Hz -4o Attenuation, db -8-0 - -. , -60 -80 (4) Curve (4): Same as Curve (1) Conditions, Light Load 4.2W Curve (5): Same as Curve (2) Conditions, Light Load 4.0 Curve (6): Same as Curve (3) Conditions, Light Load 40W -1OG 10 100 1K 10K 100K Frequency,Hz Figure 18. Measured Audio-Susceptibility Performance proceed_ only at a limited rate dictated by the output filter and other compensation networks used in the control system. For the series switching buck-regulator converter and the pulse modu- lated parallel-inverter converter, the rejection performances demonstrate little differences with respect to the loading,and are generally superior to the buck-boost converter at full load (i.e,., trapezoidal inductor current). This is easily explained by the fact that for either of these two converters, the average of the trapezoidal current is also the output load current. Inasmuch as the load resistance is kept constant during the audio test, and that the output voltage remains closely regulated, the average of the trapezoidal current is essentially unchanged. Consequently, little is re- quired for the inductor to establish an energy equilibrium during the audio test. It is for these reasons that rejection performances of the series- switching buck-regulator converter and the pulse modulated parallel converter are better than that of the buck-boost converter with each con- verter operating under trapezoidal inductor current. Furthermore, the difference between line-rejection at full load and at light load (i.e., trapezoidal vs. triangular inductor current) is relatively insignificant for the series-switching buck-regulator converter and the pulse modulated parallel-inverter converter as compared to the buck-boost converter. The converter output was monitored throughout the audio-susceptibility test. The corresponding audio signal at the converter output, plus its regular switching-frequency ripple, was within the respective peak ripple specification for each converter. 10.7 Output Impedence In the interest of defining regulation performance with dynamic loads, the output impedance was measured for the buck-boost converter and the series- switching buck-regulator, each providing a single regulated output. The measured data are plotted in Figure 19. Notice the absence of any sharp peak in the impedance curve, which signifies a well-damped transient following either a step or a sinusoidal load change. 61 Impedance, Milliohm 1000 Curve (1): Buck Boost Conv. Ei = 28V, Full Load Curve (2): Series-Switching Buck Regulator E. = 32V, Full Load 100) (2) SI I I 10 100 IK 10K Frequency, Hz Figure 19. Measured Output Impedance 62 10.8 Input/Output Isolation The dc isolation impedance is measured (1) between the input ground and the output ground for the buck-boost converter, (2) between the input ground and each output ground for the pulse modulated para- Ilel-inverter converter and (3) among the four output grounds of the parallel-inverter converter. In each case, the isolation impedance is found to be an order of magnitude higher than the specified 10 mega ohms. 10.9 Summary of Comparison Between Performance and Requirements A summary of requirements compared with capabilities for each converter is provided in Tables 15(A) and 15 (B). These data show that the converter performances meet or exceed all specification re- quirements. Certain aspects of the steady-state performances were analyzed to substantiate the measurement data. The analyses were doc- umented in the Brassboard Construction Plan [6]. 10.10 Discussion of Results 10.10.1 Output Voltage Regulation The excellent output-voltage regulation presented in Section 10.2 is due to the high dc gain (in the order of 1OOdb) analyzed in Appendix A. The output-voltage variation was caused primarily by temperature change, which affected the reference zener voltage and the voltage-divider resis- tors. Better temperature-stabilized networks for these components have been developed [3]. 10.10.2 Efficiency The efficiency goal was met by (1) carefully optimizing the loss in each functional block and (2) using the energy-recovery network. A breakdown of converter losses was calculated for each converter in the Brassboard Construction Plan [6]; measurements verify these calculations. 10.10.3 Output Current Regulation Good regulation presented in Section 10.4 is again due to the high dc gain analyzed in Appendix A. The current variation was primarily due to the error produced in the current-sensing magnetics. 63 Table 15(A) REQUIREMENTS VERSUS CAPABILITIES OF PROTOTYPE CONVERTERS Performances Buck-Boost Converter Parallel-Inverter Converter Switching Buck-Regulator Requirement Capability Requirement Capability Requirement Capability Input Voltage Range 20 to 40V 20 to 40V 24 to 40V 24 to 40V 24 to 40V 24 to 40V Audio Susceptibility 2.8V rms Output within 2.8V rms Output within 2.8V rms Output within ripple spec. ripple spec. ripple spec. Snurce Current Ripple MIL-STD-461 MIL-STD-461 MIL-STD-461 MIL-STD-461 MIL-STD-461 MIL-STD-461 Notice 3, As Notice 3 Notice 3, As Notice 3 Notice 3, As Notice 3 a design goal Met a design goal Met a design goal Met Reverse Input Protection Yes Yes Yes Yes Yes Yes Isolation Yes Yes Yes Yes No No Power Transformer Saturation -- No Saturatio No Saturation No Saturation -- No Saturation Temperature Range -25 to 850 C -25 to 850 C -25 to 850 r -25 to 850 C -25 to 850 C -25 to 850 C Voltage Regulation +0.2% +0.015% See Table 15(B) See Table 15(B) +0.2% +0.02% Efficiency 90% 90.7% 85% 85.3% 92% 92.7% P-P Output-Voltage Ripple 1% 0.85% See Table 15(B) See Table 15(B) 1% 0.55% Current Regulation +5% +1.23% None O.L. Protection +5% +0.25% Provided Brassboard Weight Ikg 0.862kg 0.75kg 0.683kg 2kg 1.629kg Load Range 0.15 to 1.5A Open to 1.5A See Table 15(B) See Table 15(B) 0.2 to 2A Open to 2A Table 15(B) REQUIREMENTS VERSUS CAPABILITIES OF PULSE MODULATED PARALLEL-INVERTER CONVERTER Regulation (%) Outputs Peak-Peak Ripple(%) Load Range (mA) Sensing IkV Sensing db/dt (Volt) Requirement Capability Requirement Capability Requirement Capability Requirement Capability 1000 0.5 0.18 30 to 40 30 to 40 + 0.2 + 0.085 + 2 + 1.83 +15 1 0.6 250 to 500 250 to 500 + 5 + 1.48 + 3 + 1.11 -15 1 0.6 250 to 500 250 to 500 + 5 + 1.47 + 3 + 1.13 + 5 1 0.9 500 to 1000 500 to 1000 + 8 + 3.16 + 6 + 1.38 SAll loads can be opened without causing any component failure. 10.10.4 Output Voltage Ripple The specified output-voltage ripple was met by properly-designed power and control circuits. Analysis substantiating the design was presented in reference [6]. 10.10.5 Source Current Ripple The two-stage filter used in this program allows the source-cur- rent ripple to be met without appreciable efficiency loss. Computer programs confirming the satisfactory filter attenuation performance were given in reference [6]. See Appendix D for design detail. 10.10.6 Audio-Susceptibility As presented in Appendix A, the high loop gain provides good audio-susceptibility performance from dc to beyond the resonance frequency of the output filter. At higher frequencies, the audio input is attenuated by the passive filter. 10.10.7 Output Impedance Low output impedance is made possible by the high gain and large bandwidth of the ASDTIC control, as well as the output-filter design with low characteristic impedance [(L/Co) /2 10.10.8 Input/Output Isolation For the buck-boost converter and the parallel-inverter converter, the impedance between the input and the output is essentially the isilation impedance of the optical coupler. This impedance is at least an order of magnitude higher than the ten megohms specified. 65 11 . CONVERTER TRANSIENT PERFORMANCE The transient response of a converter is important with regard to the following power system performances: (1) During severe line and load transients, the electrical stresses on all power-handling components of the con- verter must be controlled to within their safe operating limits. If this control is not established, the converter reliability assessment based on the statistical failure rate of individual components is of limited real value. (2) Spacecraft instrumentation and equipment loads often require a power quality which stays within a given specification during not only steady-state, but also during transient line and load conditions. (3) During a severe transient such as converter startup by command, the converter should not demand a current higher than the capability of the current-limited primary source. This is necessary in order to avoid a system shutdown due to a collapse of the source voltage. In relation to these desirable characteristics, oscillograms of waveforms were taken on all three converters under conceivable large- signal line and load changes. The waveforms included the output voltage, the power-switching current, and the source current. The following types of transients were investigated: * Converter startup by command, with output at full load * Converter startup by command, with output shorted * Converter startup by step application of input voltage * Sudden converter output short * Recovery from an output short * Step change between the specified minimum and maximum operating input voltage * Step change between the specified minimum and maximum load. 66 These oscillograms are shown in Figures 20 to 26 from which the following transient performances can be established: (1) The stress level of the power switch (and of all power components) during any line and load transients was limited to within 200% of the nominal steady-state value. The control was made possible through the design of the previously-described peak-current sensor and Digital Control Signal Processor - DCSP. (2) The design goal of meeting the steady-state 1% ripple specification during transient was met for most dynamic operations. Furthermore, all transients were critically damped, indicating good dynamic stability. During starting, there was no output-voltage overshoot. (3) The source current was always under control during large dynamic changes of line and load including sudden output short circuit. The control was enabled by the joint function of the peak-current sensor, the DCSP, and the ASDTIC current regulator. There are three traces in each oscillogram. From top to bottom, they are the source current, the output voltage, and the power-switch current, respectively. Many interesting observations can be made on the oscillograms from Figures 20 to 26. A complete identification on the nature of each wave- waveform in its minute detail is not the primary objective here. However, the following points of importance are noted for the respective figures: Figure 20, Transients During Converter Command On * There is no output-voltage overshoot during turn-on. * Initially, the peak-current sensor is limiting the power-switch current. The current regulator becomes active subsequently, which then controls the source current until voltage regulation is reached at the converter outout. 67 Figure 21. Transients During Converter Command On With Output Shorted e The zero output voltage reflects the short circuit at the con- verter output. * For the parallel-inverter converter, the IkV output is shorted. The time rate of 0.1 ms/Division does not show the automatic turn-off of the converter follwoing 20 milliseconds of switching. The turn-off is caused by the overload protection circuit described in page ie,. Figure 22. Transients During Converter Turn-On By a Step Input Voltage * The large initial source current is the charging current of the input filter. * Had there not been the damping resistor RI shown in the filter on page 105,the inrush current into the input-filter capacitors would be significantly higher. Figure 23, Transients During Sudden Converter Short Circuit * The turn-off of the parallel inverter 20 milliseconds into the occurrence of the short circuit is evident. * Of particular significance is the utility of the buck-boost converter in handling a load where frequent short circuits are expected. It can be seen from the top oscillogram that the source current never exceeds its maximum steady-state value, which is 2.3 Amperes for a 20-Volt input voltage. * The source current for the parallel-inverter converter also shows excellent performance. This is due to the joint effort of the peak current sensor and the DCSP, which effects a much! shorter on time and a lower frequency operation when the output is shorted. As a result, the average source current actually decreases slightly subsequent to the short-circuit event. 68 Figure 24 . Transients During Removal of an Output Short * The oscillograms bear resemblance to Figure 20. The only difference is the absence of any initial high peak current in either the power switch or the source when the short circuit is removed and the converter output voltage starts to build up. This is caused by the current regulator, which is already in effect due to the short circuit prior to the recovery. This was not the case during the converter "command on" in Figure 20, in which the current regulator is effective only after the initial peak-current transient has subsided. Figure 25. Transients During Step Input Voltage Change * The output-voltage excursion for the three converters are, from the top, 140 mV, 60 mV, and 4000 mV, respectively. Corresponding to the regulated output voltage of 28V, 20V, and 1000V, the excursions are within the 1%, 1%, and 0.5% ripple specification of the three converters. * No disorderly current can be observed during the input-voltage transition. Figure 26. Transients During Step Load Change * For the first two oscillograms, the transition of power-switch current between triangular waveform at light load to trapezoidal waveform at heavy load is evident. * The absence of any prolonged oscillation is in good agreement with the prediction derived from the output-impedance measure- ment shown in page 62. 69 (A) Buck BoosL Cony. (D) Buck Boost Convy. Source Current 2A/Div. 2A/Div. 20V/Div. 5V/Dtv. Output Voltage 4A/Div. 4A/Div. Output Voltage .2/Div. 5ms/Div 0.2ms/Div. Collector Current Collector Current Collector Current (B) Series Switchng ony. (E) Series Switching Conv. 2A/Div. 5A/Div. Source Current 1OV/Div Source Current 1OV/Div. 4A/Div. Output Voltage 4A/Div. Output Voltage 4ms/Div 0.2ms/Div. Collector Current Collector Current (C) Parallel Inverter Conv. (F) Parallel-Inverter Cony. 5A/Div. Source Current 50V/Di5A/Div. Source Current 4A/Div. Output Voltage 50OV/Div. IOms/Div IOA/Div. Output Voltage 0.5ms/Div. Collector Current Collector Current CONVERTER OUTPUT: FULL LOAD Figure 20. Transients During Converter Command On. Figures (D),(E), and (F) Are Expanded Views of Figures (A),(B), and (C), Respectively. (A) Buck Boost Conv. Source Current 2A/Div. 5V/Div. 4A/Div. Output Voltage Ims/Div. Collector Current (B) Series Switching Cony Source Current 5A/Div. 10V/Div. Output Voltage 4A/Div. 0.5ms/Div. Collector Current (C) Parallel-inverter Cony. Source Current 5A/Div. 50OV/Div. 10A/Div. O.Ims/Div. Output Voltage Collector Current Figure 21. Transients During Converter Command On, with the Output Load Short Circuited 71 (A) Buck Boost Cony. Source Current lOA/Div. Output Voltage 10V/Div. 4A/Div. Ims/Div. Collector Current (B) Series Switch Cony. Source Current 1OA/Div. Output Voltage O1V/Div. 4A/Div. 2ms/Div. Collector Current (C) Parallel-Inverter Cony. Source Current 10A/Div. 500V/Div. Output Voltage 10A/Div. 20ms/Div. Collector Current Figure 22. Transients During Converter Turn-on by a Step Application of Input Voltage from 0 to 40V with Output at Full Load 72 (A) Buck Boost Conv. Source Current 2A/Div. O1V/Div. 4A/Div. Output Voltage 0.5ms/Div. Collector Current (B) Series Switching Cony. Source Current 5A/Div. 1OV/Div. 4rA/Div. Output Voltage 0.2ms/Div. Collector Current (C) Parallel-inverter -Conv. Source Current 5A/Div. 500V/Div. 10A/Div. 5ms/Div. Output Voltage Collector Current The sudden interruption of collector current in the parallel-inverter converter is caused by the overload turn-off protection circuit. Figure 23. Transients During Sudden Converter Output Short Circuit 73 (A) Buck Boost Conv. Source Current 2A/Div. 20V/D iv. Output Voltage 4A/Div. l0ms/Div. Collector Current (B) Series Switching Cony. Source Current 5A/Div. Output Voltage lOV/Div. 4A/Div. 2ms/Div. Collector Current (C) Parallel Inverter Cony. Due to the fact that subsequent to an output short circuit the overload trip designed for this converter will turn off the converter completely, no recovery from a shorted load can be observed. Figure 24. Transients During Recovery from the Removal of an Output Short 74 (A) Buck Boost Conv. 5A/Div. .5V/Div. Source Current2A/Div. 5ms/Div. Output Voltage E. = Between 20V and 40V Collector Current P = Full Load, 42W0 (B) Series Switching Conv. Source Current5A/Div. O.IV/Div. 2A/Div. 5ms/Div. Output Voltage E. = Between 24V and 40V Collector Current Po = Full Load, 40W (C) Parallel-Inverter Conv. Source Current 5A/Div. 50V/Div. 4A/Div. Ei = Between 24V and 40V Po = Full Load, 60W Collector Current Figure 25. Transients During Step Input Voltage Change 75 (A) Buck Boost Conv. 2A/Di v. Source Current .5V/Div. 2A/Div 2ms/Div. Output Voltage Ei = 32V Collector Current I = Between 0.15A and 1.5A (B) Series Switching Conv. 2A/Div. .5V/Div. 2A/Div. Source Current 2ms/Div. Output Voltage E. = 32V 1 I o = Between 0.2A and 2A Collector Current (C) Parallel-inverter Convy. Source Current 5A/Div. 50V/Div. 4A/DIv. 2ms/Div. Output Voltage E. = 32V Io = Between 30mA Collector Current and 40mA for the 1000V output Figure 26. Transients During Step Load Change 76 12. RECOMMENDATIONS FOR FUTURE WORK Future work needed on the ASDTIC control system can be categorized into two areas: (1) Application, and (2) Analysis. 12.1 Application (1) Fabrication of Integrated and Microminiaturized Control Circuits The present ASDTIC program has demonstrated: (A) the versatility of the ASDTIC control concept and (B) the commonality of control- circuit modules among different types of converters. These accomplishments have greatly facilitated the future integration of the entire control circuit into either a single control module or several control modules using microminiaturization techniques. Such an integration would enhance the standardi- zation and cost reduction of power processing equipment. (2) Application of ASDTIC for High Power Converters Containing Multiple Power Modules. The need for higher converter power rating in space applications has been growing, and will exceed the capability of the avail- able high-frequency switching transistors. Consequently, it is expected that future converters involving high power (multi- kilowatt or higher) will utilize series and parallel multiple power modules. The application of ASDTIC, so far, has been limited to the control of a signal power module. The extension of ASDTIC control to multiple power modules is needed in order to enhance the technical readiness and the standardization of future high-power processing equipment. (3) ASDTIC Applications Other than Power Processing By the very nature of the analog signal to digital time interval conversion, ASDTIC could be utilized in all appli- cations where the on/off ratio of a switch is controlled as a means to achieve a desired performance. The motor speed control, in which the motor acts as a higher-order filter, is but an example of possible ASDTIC applications. 77 12.2 Analysis Power processing for space applications has, from necessity, been a rapidly evolving technology. The effort associated with nondissipative- converter analyses has been unable to keep pace with the degree of sophistication already achieved in the circuit development. However, with the capability of ASDTIC control now established, and with many ap- plications anticipated in the future, it is desirable to pursue at this time, an analytical program to achieve a comprehensive quantitative under- standing of ASDTIC control for different power converters using a variety of duty-cycle modulation techniques. The analysis should include small and large-signal stability performance, audio-susceptibility rejection, output impedance, static and dynamic regulation, and the interaction between the negative impedance of the regulator and the input filter to the converter. Specifically, the analytical results from this program would provide the following utilities: (1) To lend theoretical support to the existing high- performance dc to dc converter ASDTIC control system development. (2) To identify the optimum control system and duty cycle control mode for the most commonly used dc to dc converter and other critical power processing equipment. 78 13. CONCLUSIONS The Analog Signal to Discrete Time Interval Converter (ASDTIC), conceived originally within NASA, and reduced subsequently into minia- turized hybrid form, was utilized successfully as the controlling element for the three most commonly used dc to dc converter/switching regulators: the series-switching buck-regulator converter, the buck-boost converter, and the pulse-modulated parallel-inverter converter. The design was guided by the objectives of promoting performance and reliability improve- ments, and to achieve control circuit standardization. To achieve these objectives, a systematic design of both power and control electronics was performed, which has led to major achievements in power-circuit reliability and technology improvement, control-circuit standardization, and superior converter performances. (32) 13.1 Power Circuit Technology Improvement Power circuit technology improvements include the following features: (1) Peak-current limiting was provided for each converter to gain control of all power component stresses during steady-state and dynamic operations, thus enhancing greatly the reliability of each converter. Furthermore, the interaction between the converter and the primary power source is brought under control. (2) Energy-recovery networks were used to prevent the simultaneous occurrence of high voltage and high current in the power tran- sistors and to recover the energy stored in the transformer leakage inductance, thus eliminating transistor secondary breakdown and reducing switching losses. (3) Optimum weight and efficiency were achieved through (A) the design of magnetic components based on a set of minimum weight equations, (B) elimination, through active means, of high current spikes due to saturation of the parallel-inverter converter power transformer, and (C) the use of a proportional current drive, energy recovery network, and a two-stage input filter. 79 13.2 Control Circuit Standardization The control circuit standardization includes: (1) Adoption of the ASDTIC microminiaturized control module to the three dc to dc converters led to uniformly outstanding static and dynamic regulation as well as control loop stability. (2) Commonality was also attained in the control loop interface circuits of the three converters. This was achieved through a novel Digital Control Signal Processor (DCSP) design, adaptable to all dc to dc converters. Utilizing a total of only seven parts, the DCSP processes all control requirements including (A) interface with ASDTIC voltage and current regulators, (B) provision of duty-cycle control with either a constant on-time, a constant off-time, a line-dependent variable on-time, or a constant frequency, (C) processing of the peak current protection for the power switch, (D) response to on/off command and enforcing an orderly converter startup, and (E) synchronization to an external clock frequency, if needed. (3) To facilitate standardization, control circuit submodules were divided in accordance with their respective control and pro- tection functions to enhance maintainability, interchangeability, and subsystem circuit block identification. 13.3 Performances One breadboard and two brassboard demonstration models were fabricated and tested for each converter. All specified steady-state efficiency, ripple, and regulation requirements were either met or exceeded. Out- standing were precision voltage regulation (within the vicinity of +0.02% over a two-to-one input line change, open to full load output change, and a temperature range of -25°C to + 850C). Ihe good transient performances as reflected in the oscillograms presented in this report are excellent. The power switch current, the source current, and the output voltage are controlled under all dynamic operations. In fact, the 1% peak voltage ripple 80 includes not only that of the steady-state, but also the voltage excursion during these non-concurrent dynamic conditions: (1) converter starting, either switch-on or command-on, (2) resuming regulation following the removal of an output short circuit, (3) a step change between minimum and maximum input voltage, (4) a step change between 10% and 100% full load, and (5) a 2.8V rms superimposed on the converter dc input voltage during the audio-susceptibility test. In summary, the ASDTIC microminiaturized control module and control system were demonstrated to be applicable for controlling the three most commonly used dc to dc converters, with superior static and dynamic per- formance. New technology was developed and applied to improve reliability and to achieve optimum converter weight and efficiency. Commonality of signal functions for all converters, enabled by the ASDTIC control module and the new Digital Control Signal Processor design, facilitates the standardization of future high-performance dc to dc converter regulation, control, and protection circuits. 81 APPENDIX A SMALL SIGNAL ASDTIC OPEN LOOP FREQUENCY RESPONSE Al. Frequency Response The ASDTIC two-loop control performs the regulating function through discrete pulses generated by the nonlinearity of pulse width modulation. A precise small-signal analysis encompassing the entire A-to-D-to-A process from dc to switching frequency of the converter would require extensive analytical modeling and simulation technique. Such an effort was, unfortunate- ly, beyond the scope of this application-oriented development program; it was identified as a future task in section 12 of this report. In an attempt to gain at least some qualitative insight into the ASDTI.C control system, an analysis based on a low-frequency linear model was carried out for a series-switching regulator to access the control system's frequency response. The control circuit diagram is shown in Figure 27. Using the symbols designated in this figure, the open-loop freauencv response can be shown to be: cs) = o C s) cs) Ies) (Al) O(s) = I + SPC "* R S Z a k >+R - e+ PC. C,, C , R (Ar) denominator, and y(s) represents the stabilizing effect provided by loop 1 1+ R4 R5 + Rdc) I in tegrator-amplifier characteristic, with its time constant denoted in theI. denominator, and y(s) represents the stabilizing effect provided by loop I in conjunction with loop II. 82 A Rdc LNA o Eo 0 on timeTn , NB NB Co RR off time,Tf D1 NA R PLI R1 R4 C INTEGRATOR LOOP I AMPLIFIE THRESHOLD B + DCSP : s+_DETECTOR " R3 ET C2 R2 K : Small-signal gain e= R=from B to A clockwise Figure 27. Block Diagram of ASDTIC-Controlled Series-Switching Buck Regulator oo This response is sketched in Figure 28. The five points designated as point "a" to "e" are related to equations (Al) to (A4) as the following: (A) The amplitude of point "a" is determined by the numerator of equation (A3), the dc gain. (B) The frequency at point "b" is determined by the denominator of equation (A3),.the corner frequency at the integrator amplifier. Between "b" and "c" the gain decreases at -6db/octave. (C) Point "c" represnets the L0 C filter resonance shown in the denominator of equation (A2). Between "c" and "d" the gain decreases at -18db/octave if the damping term (i.e., the "S" term) in the denominator ofd(S) is small. (D) The frequency at point "d" is determined by the S2 term in equation (A4). Between "d" and "e", the gain decreases at -6db/octave. (E) Point "e" represents the unity-gain point with a -6 db/octave slope. A2. Discussion of Analytical Results Several important observations can be made as the following: (A) The immunity of stability to filter components L C : The effect of L C on the frequency response is reflected by points "c" and "d", based on the S2 term in the denom- inator of equation (A2) and in equation (A4). Any change in Lo or Co tends to move these two points of Figure28 in the same direction (e.g., points c'and d', thus compensating each other and leaving point "e" unchanged. The stability is, therefore, not affected. (B) High Gain, Large Bandwidth, and Precision Regulation The dc gain is represented by the product involving the numerator of equation (A3). Since the open-loop dc gain of the operational amplifier, K, generally exceeds 100db, the converter dc loop qain is extremely hiqh. Furthermore, the second order filter effect is eliminated by the y(s) term of eq. (A4) for frequencies higher than point "d". The extension of the -6 db/octave slope from "d" to "e" greatly increases the bandwidth of the converter. 84 a=V c With C -6db/octave . d -6db/octave Without C e Frequency, Hz Fiqure 28. Open-Loop Frequency Response of the ASDTIC Control (C) Stability of the Two-Loop Control System From the numerator of equation (A3) the increasing dc gain as a function of R4 (for a given R3 ) becomes evident, which results in better static reg- ulation performance. However, the (R4/R 3) ratio in the s2 term of equation (A4) suggests a migration of point "d" toward a higher frequency when (R4/R 3) is increased, thus creating an extended frequency band between point "c" and "d", within which the roll-off rate is at -18db/octave. The fast roll-off results in a Doorer phase margin. Ideally, the (R4/R 3 )ratio should be designed with Doints "c" and "d" to coincide so as to mitigate this undesirable situation. The -6db/octave slope between "c" and "e" thus maintains converter stability. (D) The Necessity for Capacitor C in Figure 27 The negative peaking at the frequency corresponding to point "d" increases drastically with a reduction in C. The peaking amplitude is determined by the damping term (i.e., the "s'' term) in equation (A4). The addition of capacitor C in Fig.27 serves to increase the damping of y(s). Without C, the deterimental effects associated with the peaking would include: (A) prolonged ringing at a frequency corresponding to "d" subsequent to sudden line and/or load changes, and (B) degraded audio-susceptibility performance within a frequency band centered around point "d". This frequency, Fn, can be expressed as the following: 85 APPENDIX B MINIMUM-WEIGHT TOROID-CORE INDUCTOR DESIGN EQUATIONS BI. Introduction The design of a toroid inductor is normally achieved rather routinely. Based on information concerning the inductance L needed, the peak curent I through it, and the saturation flux density Bs of the core material, the designer starts with a core having area A, mean length z, window area A., and permeability p. The number of turns N needed to make inductancd L is then calculated. At this point two comparisons are made: (1) NI p/z = pHp is compared to Bs to see if the magnetic capability is fully utilized, and (2) N is multiplied by A (i.e., A being the sectional area c c of copper per each turn of conductor as required to handle the winding current with peak value I p) to see if the window area Aw is sufficient to accomodate the windings, from which the relative value of A with respect to NA /F = A , where F is the estimated winding factor, is determined. Six possibilities would emerge from these comparisons, namely; (A) pH >B , A >A , (B) IH >B , A A p s x w p s. x w p s x w (D) pH 5.5 should be used. In actual design, NC = 5 rather than NC = 6 is used as it generated less loss. The selection is supported by experimental observation, which shows that no saturation current is observed in the converter breadboard throughout the line, load, and temperature range. It is noted that such a performance is 94 achieved without overdesign of the transformer flux capability, as both cores are used very close to their full extent. A decrease of NC from 5 to 4 definitely produces saturation current at high temperature, high input, and full load. C3. Other Discussions The following points concerning the two-core transformer should be noted: o To a first degree of approximation, the conduction time of the transistor is inversely proportional to the input voltage with this transformer configuration is being used. o The transformer core will determine the operating Tn; any on-time interval set by the pulse stretcher of the the DCSP will have to be longer than the operating Tn in order not to interfere with the intended operation of the two-core transformer. o While the transformer is free from any saturation current at the end of a conduction half cycle, its function does not include the suppression of charging current into the transformer winding capacitance at the start of a conduction half cycle. This charging effect is more pronounced for high-voltage converters such as the subject converter, which includes IkV as one of its output voltages. o Depending on the initial flux level for the two cores, transformer saturation may occur at the end of the first half cycle of converter operation following the converter turn-on. However, the saturation current is still limited by the peak current sensor discussed in the report. 95 APPENDIX D A TWO-STAGE INPUT FILTER WITH NONDISSIPATIVELY-CONTROLLED DAMPING Dl. Introduction In space applications where switching regulators are frequently employed, an input filter is normally required between the regulator and the power source. The filter serves two functions: 1) to prevent the alternating current component generated by the regulator switching from being reflected back into the power source having high source impedance, and 2) to isolate line-voltage transients in the source so as not to degrade the performances of the switching regulators downstream. Consequently, the filter is re- quired to provide not only high attenuation at the switching frequency of the regulator, but also sufficient damping against any line disturbance so that output peaking is properly controlled at the resonant frequency. In conjunction with the ever-present requirements of small filter size, weight, and loss, a satisfactory filter design becomes rather difficult to achieve without trading one or more performance characteristics for the others. For example, a conventional LC filter can be highly efficient due to a low damping factor, yet resonant peaking is very high. During severe line transients, such as a step change of the source voltage (including the sudden connection of the source voltage to an initially relaxed filter), the peak transient output voltage across capacitor C may reach a dangerously high level. The damping factor of the filter can be easily increased by introducing resistance R to bring the resonant peaking under control. However, since most of the pulse current drawn by the switching regulator must now encounter R, the efficiency of the filter is greatly reduced. Described in the following is a two-stage filter capable of providing low loss, high attenuation, and a controlled resonant peaking. The filter 96 is particularly useful for regulated converters having such stringent efficiency, attenuation, and peaking requirements that conventional single- stage filter systems would simply become either inapplicable or impractical with respect to size and weight. The two-stage input filter power circuit was presented in page 46 of this report. The following descriptions include component selection guidelines, transfer-function analysis, and design procedures. D2. Component Selections The following guidelines can be observed in selecting filter components: (1) Since C2 supplies the majority of the pulse current required by the switching regulator, the use of low-dissipation capacitors is desirable. Various types of capacitors are likely candidates including mylar, polycarbonate, and polysulfane. (2) Inductor L2 supplies a minor portion of the alternating current. The use of molypermalloy power-core material for small core loss is, thus desirable. (3) Capacitor Cl handles very small alternating current during steady- state operation. Foil, solid, and wet-slug tantalum capacitors are suitable for Cl. (4) During steady-state operation when the switching frequency is much greater than the filter resonant frequency, the resistor RI encounters negligible current. Practically any type of resistor can be used for Rl. However, the resistor should have a peak power capability to handle the current inrush due to a step change in the source voltage E. such as when E. is sudenly applied to an initially relaxed filter. (5) Inductor Ll passes essentially a direct current corresponding to that required by the s'.itching regulator. Eddy-current and hysteresis losses are thus of negligible concern. However, design experience indicates that when a higher saturation flux core material such as gapped silicon steel is used for size and weight savings, the small ad handled by Ll seemed to incur enough core loss to place an equivalent resistance across Ll. At the switching frequency of the converter, the resistance may be of such a low value as to cause a degradation of filter attenuation capability from its designed performance level. 97 D3. Filter Transfer Function By solving two loop equations for the two-stage filter, its transfer function G(s) can be derived as ea I-t 3 c I Re e -t S CI, Three frequencies of particular interest are: (1) the first-stage filter resonant frequency fl, (2) the second-stage resonant frequency f2, and (3) the regulator switching frequency F. (1) At fl where S2 L1 C1 = -1, the magnitude of G(S), or peaking at fl' can be derived to be: I+z Here, D is the damping factor of the first stage, i.e., R,D ) (2) At f2 where S2 L2 C2 = -1, the second peak of G(S) can be derived to be: q (D3) The resonance of the high-Q second stage is, thus, effectively clamped to a value corresponding to L2/L1 by the presence of the first stage. Since L2/L 1 < I is normally observed, peaking beyond 0-db is, therefore, impossible. (3) At F, where F >> fl and F >> f2, it can be shown that the value of /G(s)/ becomes r2 C 98 Solving for approximate (F/f ) , F A I C f( ) f, zfz D4. Design Procedure The following general observations to aid in the design of a two-stage filter can be make: o The factor L2 /L1 should be less than unity to avoid the second- stage peaking defined in eq. (D3). 'In typical designs, L2 /L = 0.25 to 0.5 is common. o In conjunction with (f /f 2 ) = L2 C2 /L 1 C1 , the factor C2 /C should be sufficiently small to permit a positive real solution for D in eq. (DI). Solving for D z - p, ( ca/cz i CC/c,) - 4 CS) For example, let Pl2 = (i.e., P = v* for a + 3db peaking), and L2/L l = 0.25. It is then necessary that 21.5 I C- ( Io+)S >.5 ( C 5 in order for D2 of eq. (05) to be positive. Thus, C, In actual design, C2 /C i less than 0.225 should be used to achieve a reasonable value of D that is not exceedingly large. Typically, C2/C l ranges between 0.05 to 0.1. Using these design equations, the following step by step design procedures can be explained: 1) Calculate the maximum rms current in C2 based on given line and load conditions including overload requirements of the switching regulator. 99 2) Based on this rms current, choose the capacitors for C2. With the capacitance of C2 selected, a check is make to ensure that the maximum steady-state ripple voltage across C2 is not excessively large. If the calculated result proves otherwise, C2 should be increased accordingly. 3) The ratio of L2/LI and C2/C l can be chosen to achieve a given attenuation at a specified frequency for as long as they are consistent with the afore-described general observations. Some recommended ratios are given here as functions of attenuation, AT. 20 log 10 AT (i.e., db) -40 -60 -80 -100 L2/L1 1/3 1/4 1/4 1/4 C /Cl 1/10 1/15 1/15 1/20 (f!/f2)2 1/30 1/60 1/60 1/80 4) With C2/C l and L2/LI chosen, eq. (D5) can be used to cal- culate the damping factor D in order to limit the resonant peaking to the specified Pl, i.e., the magnitude of the first peak of G(S). 5) In conjunction with a given set of A and F, eq. (D4) is applied to calculate fl. 6) Determine L1 from 7) From eq. (D2) and the selected L2 /L1 ratio, calculate R and L2. D5. Effect of Regulator Negative Impedance on Input Filter Performance The effect of regulator negative impedance on the input-filter performance was discussed in the literature. [311 The discussion was limited to the possible van del Pol type of oscillation when an improperly design filter is matched to the regulator. 100 Another effect of regulator negative impedance is to degrade the audio- susceptibility performance. The input filter for the parallel-inverter converter is used as an example for illustration. A voltage of IV rms is applied to the filter input terminal. The filter output supplies a resistor; the negative resistance representing R is simply -E. /P., where E. is the converter input voltage, and P. is the converter input power [31]. For the parallel-inverter converter, (E.)m = 24V and (P.) m 70W, giving R % -8.2 ohms.I min max = With Ll = 381 pH, L2 = 127 pH, C1 = 200 pF, C2 = 20 VF, and RI = 3 ohms, the audio performance of the filter was calculated by a computer, first using R = - and then using R = -8.2 ohms. Analytical results are sketched in Figure 29in which the impact of the regulator negative resistance on the filter audio performance is evident. The additional peaking due to the presence of the negative regulator resistance was not treated in the analysis of Section D3, as the added component would make the transfer function too complicated to gain any analytical insight. Nevertheless, the equations derived and the design procedure generated still serve as a convenient design tool to meet a required source-current ripple specification. However, the actual filter resonant peaki.ng as a result of the negative-resistance load will be higher than those predicted in equations (DI) and (D3). Using the afore- described filter as an example, the audio-susceptibility data with and without the negative resistance, as calculated by a computer,is presented in Figure 29. Two additional subtleties involving filter-regulator combinations are noted: (1) It is, in reality, a negative "impedance" rather than a negative "resistance" that the converter reflects. Over the audio frequency spectrum, the "impedance" may closely resemble a "resistance" only at low frequencies when the open loop gain of the regulator is high. (2) If the Bode plot of the regulator loop reaches unity gain before the filter resonance-peak frequency, then there is no negative impedance at the filter resonant frequency. Under this circumstance, the re- sonant peaking of the filter supplying the regulator would be approx- imately the same as predicted in Eq. (DI). 101 ATTENUATION db +10 / with the reflected Vnegative resistance without the reflected negative resistance -10C- -20 - -3C - -5C - -6 I I 100 500 1K 5K 10OK 50K 1OOK FREQUENCY, Hz Figure 29. Input-Filter Frequency Response With and Without the Reflected Negative Resistance From the Converter-Regulator APPENDIX El Table 16. POWER CIRCUIT COMPONENTS AND PARAMETERS POWER CIRCUIT BLOCKS BUCK-BOOST CONVERTER SERIES SWITCHING CONVERTER PARALLEL-INVERTER CONVERTER Reverse Input Protection Fl : 5A fuse CR1 : IN5627 Same Same Lnput : L744, 381H L1 : L744, 381pH L2 : L71OA, 1271 H L3 : L710A, 127pH Ri : 3n, 5W Rl : 3n, 5W Cl : O0F, 75V Same as Buck-Boost Converter ,C2 : , 75V each C2 : 10pF, 50V C3,C4 : 10F, 50V each T1 : L688B Tl : L688B T3,T4 : L688A VRI : JAN IN759A VRI : JAN IN759A VRI, 2 : IN759A Peak-Current Sensor CR2 : IN3604 CR2 : IN3604 CR15,15 : IN3604 CR3 : JAN IN4942 CR3 : JAN IN4942 R6,R7 : 1400, 1W R2 : 221o, 1W R2 : 422p, 1W U53 : MC680P RIO : TS (Test Selected) RIO : TS L4 : L697 L3 : L746 L3,L4 : L697 Energy Recovery Network CR5 : IN9050D CR5 : JAN IN4942 L5,L6 : L706 CR6 : JAN IN6942 CR7,8 : PD9050E C4,C5 : 0.O1vF, 300V, Glass CR2-6 : JAN IN4942 CR5-8 : O.01pF, 300V, Glass T2 : T980A T2 : T980C TI,T2 : T983C Q3 : JAN 2N2222A Q3,Q4 : JAN 2N2222A CR4,9 : IN3604 Proportional Current CR7 : IN3604 CR6,7 : IN 3604 Q3,Q5 : 2N2851 Drive R3 : 10K, 1/8W R2,R4 : 2K, 2W R4 : 2K, 2W R4 : 10OK, 2W R3,R5 : IK, 1W R5,R6 : IK, 1W C4 : l00pF, 200V L5 : L966C, 220 H L4 : L704A, 250pH L7 : L753Q2 : PT9310, TRW Q2 : 2N5660 L8 : L761A,700mHBasic Power Circuit CR8 : JAN IN4942 CR12 : PD9050D L9,10 : L712A, 1.25mHConfiguration CR9,10 : PD9050D C5-C7 : 100F, 50V, each Lll : L713A, 0.53mH C8-C13 : 100F, 50V, each T5 : T992D Q2,Q4 : PT9310 Z1 : 652-827, Unitrode CRI2,13 : JAN IN4942 CR16-19 : PD9050D CR20,21,28,29: PD9050A C9 :.25uF, 20V CO1 :10.1lpF, 1.5kV CII-14 : 22pF, 50V, each C15,16 : 100F, 20V, each C APPENDIX E2 Table 17. CONTROL CIRCUIT COMPONENTS AND PARAMETERS Control- Circuit Blocks Buck-Boost Converter Series Switching Converter Parallel-Inverter Converter R71,R73 : 39.2K, 1/lOW C71 : 10pF, 20V R71,73 : 51.1K, 1/lOW C71 : 10F, 20V R12 : O10M, 1W C71 : 2200pF, 200V R72 : 10K, 1/1OW C72,76 : 15F, 50V R72 : 10K, 1/lOW C72,76 : 15uF, 50V R13 :120K, 1/4W C72 :6.8pF, 35V ASDTIC R74 :43.2K, 1/lOW C73 :2200pF, 200V R74 :28.7K, 1/10W C73 :2200pF, 200V R14 : 100K, 1/2W C73 :0.022vF,100V Voltage R75 :16.2K, 1/20W C74 : O.039vF,O100V R75 :16.2K, 1/20W C74 :0.022pF, 100V R71,73 :46.4K, 1/lOW C74 : 0.047vF,200V Regulator R76 :TS, 1/20W C75 : LpF, 50V R76 : TS, 1/20W C75 : 1PF, 50v R72 : 10K, 1/lOW C20 :250pF, 1.5kV R77 :21.5K, 1/lOW U71 :X254814,TRW R77 :14.7K, 1/lOW VR71 :PT4-2273 R74 :5.49K, 1/lOW U71 :X254814,TRW CR71,72 :JAN IN4942 VR71 :PT4-2273 R78 :4.02K, 1/lOW CR13,71, JAN IN4942 R75 : 8.06K, 1/lOW CR22-25 :JAN IN4942 72 R79 :15K, 1/8W U71 :X254814,TRW R76 :TS, 1/lOW L12,13 :L 754 R77 : 120K, 1/4W VR71 : PT4-2273 R78 :TS, 1/10W CR71 :IN 5297 R53 : 200K, 1/8W C51 : 47pF, 200V R53 :200K, 1/8W C52 : 1500pF, 200V R54 : 1K, 1/8W C52 : 1500pF, 200V R54 : 1K, 1/8W C53 : O.luF, 100V ASDTIC R55 :25.5K, 1/20W C53 :0.luF, 1OOV R55 : 100K, 1/lOW VR51 :PT4-2273 Current R56 :23.7K, 1/20W VR51 : PT4-2273 R56 :22.1K, 1/20W T3 :T967B Regulator R57 : 2K, 1/20W T3 : T965A R57 2K, 1/20W T4 T966A None R58 : 4.32o, 1W CR8,11, JAN IN4942 R58 : l0, 1W CR8-11 : JAN IN4942 12 R59 : 5110, 1/20W R59 : 4320, 1/20W U51 : MC680P R60 : TS, 1/20W U51 : MC680P R60 : TS, 1/20W U52 : uA 741 U52 : RA2909 R101 : 1K, 1W ClOl : 0.O F, 200V R102 : 16.5K, 1/20W nput/Output R102 :4.75K, 1/20W C102 :33j, 10V C102 : 2 .2pF, 20V Isolation R103 :1.33K, 1/20W VR101 :FCT 1122 None CR101 :None R104 : 240K, 1/8W Ul01 : LM3110 CR26,27: JAN IN4942 R105 : 56.2o, IW U102 : MCD2 L14 : L755 CR101 : JAN IN4942 U103 : MC679P All other components same as the buck-boost converter. Digital R91 : TS, 1/lOW U91 : MC675P R92 : 56.2K, 1/lOW R97,98: 15K, 1/lOW U92,94 :MC675P Control R92 : 68.1K, 1/10W U91 : MC670P C91 : 330pF, 200V C92,93 : 0.022uF, 100V U93,95 : MC660P Signal C91 : 1500pF, 200V U93 :MC672P C92 :3300pF, 200V C94,95 :820pF, 200V U96 :MC672P All others same as the buck-boost converter U97 : MC679P R31 : 4.320, 1W C31 : 47pF, 200V Series R32 : TS, 1/20W C32 : 15,F, 20V Same Same Regulator R33 : 84.5K, 1/20W CR31 : JAN IN4942 R34 : 20K, 1/20W U31 : LM205H Q1 : 2N4900 R51 : 10K, 1/8 C51 : 6.8F, 35V R52 : TS, 1/20W C52 : 1500pF, 200V R53 :61.9K, 1/lOW C53 : O.IF, 1OOV Overload Pro- R54 : 11K, 1/20W C91 :33F, 20V tection, None None R55 : 47.5K, 1/20W U51 : MC680P Undervoltage R56 : 39.2K, 1/20W U52 : RA2909 Protection, R57 : 2K, 1/20W U53 : MC680P Power R91 :9.09K, 1/20W U91 : A741 Magnetics R92 : 7.5K, 1/20W R8,10 : 10K, 1/8W Saturation R93 : 8.66K, 1/20W R9,11 :5600, 1/4W Sensor R94 : TS, 1/20W VR3,4 : IN965B R95 : 1K, 1/20W CR51,52: IN3604 R96 : 75K, 1/20W APPENDIX F DESIGN CRITERIA AND DESCRIPTION OF POWER CIRCUIT FUNCTIONAL BLOCKS SKETCH OF POWER CIRCUIT BLOCKS CIRCUIT DESCRIPTION DESIGN CRITERIA The protection is accomplished by isolating the (A) FI shall not blow during slow converter startup. REVERSE INPUT PROTECTION input source and the converter through the open- (B) Fl shall blow before CRI in case of a reversed ing of fuse Fl when a negative voltage is in- input. Fl advertently applied to the converter. STo Converter (C) FI shall not blow during a step converter start. The majority of the inrush current during converter startup is the charging current to Cl and C2, when CRI Ll and L2 saturate. This current is maximum when the input step voltage is the highest. With the application of a 40V step input, and with nonlinear saturable inductors, a computer program was used to solve for inrush current. Comparing the analytical result to the blow-time curve of the fuse led to the conclusion the fuse will not blow in this worst case. INPU T FILTER The first filter stage withLl-Cl-RI controls the (A) Meet MIL-STD-461A (N3) Conducted interference. resonant peak of the filter responding to the (B) Sufficient damping for limited resonance peaking. Ll L2 specified 2.8V rms audio-frequency input voltage. 0 u The second stage L2-C2 supplies most of the (C) No oscillation when coupled to a regulated con-T pulse current required by the buck boost power verter (i.e., a negative impedance). Cl2 configuration at switching frequency. The ac C2 component of the pulse current can be attenuated Design procedures, supported by a computer program, RI by the combined action of both filter stages to are shown in Appendix F. meet the prescribed conducted interference level. Using a high-quality polycarbonate capacitor for C2 results in very little power loss. With C2 providing essentially all the ac component of the pulse current, negligible current flows in Cl and RI during steady-state operations. Control of resonant peaking is,thus,achieved without degrading the converter efficiency. PEAK CURRENT SENSOR Instantaneous current in Q2 is sensed by current The sensor will not interfere with the normal steady- transformer TI, and is reproduced as voltage state operation when there is no excessive peak current. V across R2. During the off time of Q2, reset Therefore, with threshold voltage level E , the design _ _ _ -To Power R2 Tl Switch Q2 of core TI is accomplished through winding 3-4, should be: diode CR2, and a separately generated reset N R2 (I v* af t CR2 oltaqe (12V). Voltage VR2 is coupled (VR) P max 5Ous n E - ET SAPPENDIX G4 o pESIGN CRITERIA AND DESCRIPTION OF DCSP (CONT'D) FROM PEAK CURRENT SENSOR FROM POWER MAGNETICS FRCM VOLTAGE REGULATOR SATURATION SENSOR THROUGH INPUT/OUTPUT ISOLATION 12V o A LOGICAL I1 A TURNS Q4 OFF ---- v .7 R97 C92 T BC 8 D-I -- GICAL TURNS Q2CFF R98c9TT ._.___-*FROM OVERLOAD &C93 UNDERVOLTAGE SENSORS FROM PEAK CURRENT SENSOR c FROM POWER MAGNETICS SATURATION SENSOR PULSE STRETCHER (1) PULSE STRETCHER (3) ND (5) ND (1) ND (3) PULSE STRETCHER (2) PULSE STRETCHER (4) ND (6) ND (2) FLIP FLOP (2) ND (4) TWO-CHANNEL DIGITAL CONTROL SIGNAL PROCESSOR APPENDIX G5 DESIGN CRITERIA AND DESCRIPTION OF PARALLEL-INVERTER CONVERTER PROTECTION CIRCUITS COW KOL CIKRUIT BLOCKS CIRCUIT DESCRIPTION uESIGN CRITERIA OVERLOAD AND UNDERVOLTAGE Instead of designing an active current regulator on each (A) The RC network between the flip-flop and the PROTECTION FOR PARALLEL- of the multiple outputs, which will increase significantly integrator amplifier is needed to prevent a INVERTER CONVERTER ONLY the parts count of the converter, an average "input cur- false turn-off when there is only a high input rent limiter" is selected. current transient. It was decided that a 20ms time interval is sufficiently long to identify Ei The instantaneous input current in each power transistor a true overload. The F51 time constant is is accurately represented by the voltages across resistors therefore designed to dscharge cfrom E R6 and R7 of the respective peak-current sensor and,there- (i.e. the bias supply) to E (i.e., the flip- fore, is conveniently available without additional sensing (i.e., the bias supply) to ET (i.e., the flip- network. These two voltages are summed to appear across flop threshold) in 20ms. Using R57. Derivation of VR6 and VR7 can be seen in Figure 10. RC = 20 x 10- 3 R 4 The unidirectional voltage pulse across R57 is averaged by EK R51 the operational amplifier U52 with a time constant R54C52, T 6V and compared to a reference set by zener VRlO1 (of the in- R55 R7 put/output isolation), resistors R55' R53, and R52 , and and with EK = IV, ET = 8V, the RC time con- capacitor C53 . The logical-i signal at the output (pin 6) stant is found to be about 66 x 10 -3 seconds. of U52 becomes instantly logical-O when the input current Inactual design, = 10K and C 1 = 6.8Fwere C51 reaches the reference level. Neglecting the effect of R5 1 chosen. C53 5 52 - and C5 1 for the time being, the logical-O signal is applied (B) Capacitor C91, used in the UV protection, to an R-S flip-flop, pin I of U51. serves multiple purposes: O The undervoltage protection is implemented to prevent any (a) In conjunction with input E. and resistors - VRIOI uncontrolled converter startup characteristics under a R91 through R94, the capacitor creates a time slowly-increasing input voltage. The input voltage is constant when the converter is "knifed" on. A U51 sensed, and compared with reference VRIOI through a compar- Since the 12V logic bias supply is not availa- 3 Q ator U91. When the sensed voltage is below the reference, ble at the instant of knife-on, no converter FLIP a logical-O signal is applied to pin 4 of ND(3) and pin 12 startup is possible in the absence of C91, as of ND(4), keeping Q2 and Q4 off. A logical-i signal, of the overload-protection network will always B FLOP course, releases this inhibit when the input becomes suf- act to disallow a normal startup. Capacitor 7 ficiently high. The output of U91 also feeds pin 5 of C91 thus accomplishes the function of delaying the flip-flop. The output of the flip-flop, Q, is coupled the converter turn-on following the input-vol- into pin 5 and Pin 13 of the last NAND gates ND(3) and ND(4). tage knife-on until a 12V is charged across C51 of the overload protection network. R 2 & R91 (b) Capacitor C91 also absorbs whatever mech- U1 OE. anical bouncing that may occur when the con- R95 verter is turned on, either through a knife-on or a command-on switch. R96 o To R3 I Pin 4 of ND(3) Pin 12 of ND(4) APPENDIX G5 DESIGN CRITERIA AND DESCRIPTION OF PARALLEL-INVERTER CONVERTER PROTECTION CIRCUITS (CONT'D) CONTROL CIRCUIT BLOCKS CIRCUIT DESCRIPTION DESIGN CRITERIA OVERLOAD AND UNDERVOLTAGE The behavior of Q can be summarized as the following: This description suggests that the time constant PROTECTION FOR PARALLEL- involved in charging C91 from zero to E (the ref- INVERTER CONVERTER ONLY FAULT WITHOUT OVERLOAD WITH OVERLOAD erence level of the undervoltage detecru) should be erence level of the undervoltage detector) should be(CONT'D) CONDITIONS longer than that required to change C5 1 from zero to Without under- A = I A = 0 Eru(the threshold level of the R-S flip-flop in the voltage B = 1 B = 1 overload protection network). Mathematically, the IConver- design can be expressed as: ter OFF E. REFER TO SKETCH ON With under- A = 1 A = 0 C I(Rg91 + R92)ln E.-E (1 + P) THE PREVIOUS PAGE voltage B = Conver- B = 0 Conver1 + P ru C 51 1n Iter OFF ter OFF I + P T-ET = I Q = Inde min- Q (R9 1 + R92 )(R9 3 + R94 ) P= With the R-S flip-flop and the NAND gate (of R 93R94 the DCSP) working in unison, no converter switching can occur in the event of an undervoltage at the conver- ter input or an overload at the converter output. Since the overload protection acts essentially as an average input-current threshold detector, proper means and the frV is the effective bias supply voltage, must be incorporated to prevent the overload protection i.e., the 12V bias less an internal diode drop. from false triggering during short transient, such as (C) Since the protection network detects the average converter starting and sudden line or loading changes, input current as a voltage across R and compares when the input current may temporarily register a it with a fixed reference, a larger power dissipa- higher level than the reference. It is for this reason occur for a higher input voltage. To that R and C were added. Whenever an apparent over- tion would occur for a higher input voltage. To load o curs, w ch may be real or unreal, capacitor C prevent this linear increase of power dissipation,load51 resistor R56 is added between the converter input will maintain a no-trip voltage for a sufficient time 56 interval to delay Q from being a logical-O. Thus, in and R57 The divider action of R56 and R5 7 as the this way, short transients are overlooked by the over- converter input voltage is increased, causes the load protection, and sources of false triggering are protection network to trip with a lower input avoided. During this delay time, the stress on the current. power transistor is limited by the peak current sensor (D) Once the overload protection is triggered by a and the energy-recovery network. (D) Once the overload protection is triggered by ah eco y w true overload of sufficient duration, the conver- ter wi 11 turn off. A reset of the turn-on command is needed to restart the converter. No restarting can be achieved unless the overload is cleared. APPENDIX H NOMENCLATURES A Cross-sectional area of core, m2 AC Copper conductor area per turn, cir mil A Filter attenuation requirement, db AW Window area of toroid core, m2 AI Integrator amplifier internal rolloff frequency, Hz Bp Peak flux density, weber/m2 BS Saturation flux density, weber/ m2 Co Output capacitor, pF D Damping factor Dc Density of copper conductor, Kg/m 3 D. Density of magnetic core, Kg/m 3 e Efficiency eo Instantaneous converter output voltage, V eol Loop I signal voltage, V eo2 Loop II signal voltage, V ED Threshold-detector output voltage, V Ei Converter input voltage, V El Integrator output voltage, V EK Logic bias voltage,regulated, V EL AC inductor voltage, V Eo Average converter output voltage, V Ep Pulse-generator output voltage, V ER Reference voltage, V Eru Reference level of under-voltage detector, V ET Threshold level, V F Converter switching frequency, Hz F Pitch factor F Negative-peaking frequency, Hz Fw Winding factor g Voltage divider ratio of the modified ASDTIC hFE Transistor current gain iC Instantaneous source current, A IF Rated full-load current, A 123 I° Average converter output current, A I Peak transistor power-switch current, A lin DC input current, A K Integrator-amplifier open-loop dc gain, db Kd Voltage divider ratio of the original ASDTIC L Leakage inductance, 1H L Output inductor Lp Primary winding inductance, IH N Number of turns 01 Instantaneous Integrator output voltage, V Po Converter output power, W P1 First-state filter resonant peak, db P2 Second stage filter resonant peak, db Q Transistor power switch Rc Equivalent ESR of Co , ohms RK Critical load resistance for L to exhibit discontinuous MMF, ohms RL Load resistance, ohms R. Pulse stretcher internal bias resistance, ohmsIn Rdc DC winding resistance of L , ohms T Period of one cycle, sec. Tf Power-switch off time, sec. Tm Minimum off time set by the pulse generator, sec. T Power switch on time, sec. vi Permeability, Weber/ Amp-Turn Meter VBE Base-emitter voltage drop, V VCE Collector-emitter voltage drop, V W Total inductor weight, Kg Z Mean length of magnetic path, m AEo Output voltage ripple, V Alin Input current ripple, A AVr Integrator output ramp amplitude, V 124 REFERENCES [1] F. C. Schwarz, Power Processing, NASA SP-244, 1971. [2] F. C. Schwarz, "Analog Signal to Discrete Time Interval Converter (ASDTIC)," U. S. Patent 3,659,184, 1972. [3] K. K. Schuegraf and A. D. Schoenfeld, "Design, Development, and Fabrication of a Microminiaturized Electronic Analog Signal to Discrete Time Interval Converter," TRW report prepared for NASA/ERC under Contract NAS 12-2017, 1970. 14] V. R. Lalli and A. D. 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Middlebrook, "Describing Function Properties of a Magnetic Pulse Width Modulator," IEEE Power Processing and Electronics Specialists Conference Record, 1972, pp. 21-35. [151 F. F. Judd and C. T. Chen, "On the Performance and Design of Self- Oscillating DC-to-DC Converters," Proceedings of the IEEE Fall Electronics Conference, 1971, pp. 332-337. [16] F. F. Judd and H. Wilhart, "A New Self-Oscillating Regulated DC-to-DC Converter," Conference Record of Sixth Annual Meeting of the IEEE Industry and General Applications Group, 1971, pp. 807-814. [171] . M. H. Babaa, T. G. Wilson, and Y. Yu, "Analytic Solutions of Limit Cycles in a Feedback-Regulated Converter System with Hysteresis," IEEE Trans. on Automatic Control, Vol. AC-13, 1968, pp. 524-531. [181 B. E. Gladstone, "Power Systems for Satellites," EASTCON Technical Convention Record 1967, Supplement to IEEE Trans. on Aerospace and Electronic Systems, Vol. AES-3, No. 8, November 1967, pp. 511-518. [19] B. P. Schweitzer and A. B. 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Froeschile, "Two-State Modulation Techniques for Power Systems," Semi-Annual Report prepared by Bose Corporation forU. S. Army Electronics Command, Contract No. DA 28-043-AMC-02282(E). 126 [26] V. R. Lalli and A. D. Schoenfeld, "ASDTIC: A Feedback Control Innovation," Paper AIAA-72-1057, AIAA/SAE 8th Propulsion Joint Specialist Conference, November 1972. [27] G. Wester and R. D. Middlebrook, "Low Frequency Characterization of Switched DC-to-DC Converter," IEEE Power Processing and Electronics Specialists Conference Record, May 1972, P. 9. [28] J. J. Biess and D. L. Cronin, "Nondissipative Power Loss Sup- pression Circuit for Transistor Controlled Power Converters," U. S. Patent No. 3,628,047. [29] G. H. Royer, "A Switching Transistor DC to AC Converter Having an Output Frequency Proportional to the DC Input Voltage," AIEE Transactions, Vol. 74, 1955, pp. 322-324. [30] F. C. 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Solid state single-ended switching dc-to-dc converter

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Solid state single-ended switching dc-to-dc converter

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