Abstract—This paper presents a method for inferring circuit delay shifts due to bias temperature instability using ring oscillator (ROSC) sensors. This procedure is based on presilicon analysis, postsilicon ROSC measurements, a new aging analysis model called the Upperbound on fMax (UofM), and a look-up table that stores a precomputed degradation ratio that translates delay shifts in the ROSC to those in the circuits. This method not only yields delay estimates within 0.2 % of the true values with very low runtime, but is also independent of temperature and supply voltage variations. I
University of Minnesota Ph.D. dissertation. April 2010. Major: Electrical Engineering. Advisor: Chri...
The growing concern about time-dependent performance variations of CMOS devices due to aging-induced...
International audienceThis work proposes a new bottom-up approach for on-line estimation of circuit ...
Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being inte...
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation ...
The accurate prediction of the remaining useful life (RUL) of components is a major concern in elect...
This paper provides a comprehensive evaluation of the effects of Bias Temperature Instability (BTI) ...
In order to compensate RO's process, temperature and voltage variations (PVT) several CMOS effects h...
Abstract—This paper focuses on hot carrier (HC) effects in modern CMOS technologies and proposes a s...
Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow pr...
mance has become more sensitive to manufacturing and environ-mental variations. Hence, there is a ne...
Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semico...
Increasing the utility of integrated ring oscillators requires that several sources of error be add...
We report the design and characterization of a circuit technique to measure the on-chip delay of a...
University of Minnesota Ph.D. dissertation. April 2010. Major: Electrical Engineering. Advisor: Chri...
The growing concern about time-dependent performance variations of CMOS devices due to aging-induced...
International audienceThis work proposes a new bottom-up approach for on-line estimation of circuit ...
Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being inte...
Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit...
One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation ...
The accurate prediction of the remaining useful life (RUL) of components is a major concern in elect...
This paper provides a comprehensive evaluation of the effects of Bias Temperature Instability (BTI) ...
In order to compensate RO's process, temperature and voltage variations (PVT) several CMOS effects h...
Abstract—This paper focuses on hot carrier (HC) effects in modern CMOS technologies and proposes a s...
Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow pr...
mance has become more sensitive to manufacturing and environ-mental variations. Hence, there is a ne...
Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semico...
Increasing the utility of integrated ring oscillators requires that several sources of error be add...
We report the design and characterization of a circuit technique to measure the on-chip delay of a...
University of Minnesota Ph.D. dissertation. April 2010. Major: Electrical Engineering. Advisor: Chri...
The growing concern about time-dependent performance variations of CMOS devices due to aging-induced...
International audienceThis work proposes a new bottom-up approach for on-line estimation of circuit ...