This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7 % of the conventional 1:4-subsampling search, producing higher picture quality. Another feature is an optimized SIMD datapath architecture to decrease a clock frequency and an operating voltage. It has been fabricated with CMOS 5-metal 0.18 um technology. The measured power consumption to process a QCIF 15 fps video is 0.4 mW under 0.85 MHz@1.0 V
This paper investigates the power efficient motion estimation for real time video codecs. The purpos...
Research has been undertaken into domain-specific reconfigurable architectures for future System-on-...
Power-aware video coding requires a combination of highperformance and flexibility to satisfy percep...
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It feature...
A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It po...
金沢大学理工研究域電子情報学系We propose a sub-mW H.264 baseline-profile motion estimation processor for portable v...
In this paper the design of a VLSI architecture for H.263/MPEG-4 low-power video coding is addressed...
Abstract — This paper describes an 800-µW H.264 baseline-profile motion estimation processor for por...
This paper presents a VLSI macro-cell for the implementation of full-search (FS) motion estimation t...
Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile...
Due to the large amount of data transfers it involves, the motion estimation (ME) engine is one of t...
Abstract The paper presents a hardware friendly fast algorithm and its architecture for motion estim...
A key factor behind the success of video products and services is video compression that makes digit...
With reference to the new H.264/AVC video codec standard, this paper presents novel algorithmic and ...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
This paper investigates the power efficient motion estimation for real time video codecs. The purpos...
Research has been undertaken into domain-specific reconfigurable architectures for future System-on-...
Power-aware video coding requires a combination of highperformance and flexibility to satisfy percep...
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It feature...
A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It po...
金沢大学理工研究域電子情報学系We propose a sub-mW H.264 baseline-profile motion estimation processor for portable v...
In this paper the design of a VLSI architecture for H.263/MPEG-4 low-power video coding is addressed...
Abstract — This paper describes an 800-µW H.264 baseline-profile motion estimation processor for por...
This paper presents a VLSI macro-cell for the implementation of full-search (FS) motion estimation t...
Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile...
Due to the large amount of data transfers it involves, the motion estimation (ME) engine is one of t...
Abstract The paper presents a hardware friendly fast algorithm and its architecture for motion estim...
A key factor behind the success of video products and services is video compression that makes digit...
With reference to the new H.264/AVC video codec standard, this paper presents novel algorithmic and ...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
This paper investigates the power efficient motion estimation for real time video codecs. The purpos...
Research has been undertaken into domain-specific reconfigurable architectures for future System-on-...
Power-aware video coding requires a combination of highperformance and flexibility to satisfy percep...