Performance evaluation, using both analytlcal and simulation models, of circuit switching baseline networks is presented. Two configurations of the baseline networks, single and dual, are evaluated. In each configuration, two different conflict resolution strategies, drop and hold, are tried to see the performance difference. Our analytical models are based on a more realistic assumption. New analyses are given and are verified by simulation results. In single network configuration, it is shown that the drop strategy is better than the hold strategy in the case that the data transfer time is longer than I0 cycles under a high request rate. In the dual network configuration, five different communication strategies are investigated and the op...
In this paper, a mathematical method for analysis of syn-chronous packet-switching interconnection n...
The optimistic analytical results for performance analysis of buffered banyan networks are mainly du...
Multistage Interconnection Networks (MIN) are used to connect processors and memories in large scale...
This paper compares three link conflict resolution strategies applied to multicomputers with symmetr...
The design of switching systems is an important and active research area because it is essential to ...
Interconnection Networks of various designs have been proposed for use as fast packet switches for b...
A network switch is a device that connects users and providers of network services. When a user want...
The switching strategy determines the way messages visit intermediate routers. Existing evaluation s...
Multistage interconnection networks (MIN) are used to connect processors to memories in shared memor...
Abstract—The paper presents the results of a simulation study on multi-rate three-stage Clos switchi...
In order to avoid crosstalk, a new architecture is proposed for Optical Multistage Interconnection N...
Switching elements in interconnection networks for highly parallel shared memory computer systems ma...
An interconnection network system consists of layers of switching elements connected together in a p...
SIGLECNRS-CDST / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc
Previous models for performance evaluation of multistage switches have been neither accurate enough ...
In this paper, a mathematical method for analysis of syn-chronous packet-switching interconnection n...
The optimistic analytical results for performance analysis of buffered banyan networks are mainly du...
Multistage Interconnection Networks (MIN) are used to connect processors and memories in large scale...
This paper compares three link conflict resolution strategies applied to multicomputers with symmetr...
The design of switching systems is an important and active research area because it is essential to ...
Interconnection Networks of various designs have been proposed for use as fast packet switches for b...
A network switch is a device that connects users and providers of network services. When a user want...
The switching strategy determines the way messages visit intermediate routers. Existing evaluation s...
Multistage interconnection networks (MIN) are used to connect processors to memories in shared memor...
Abstract—The paper presents the results of a simulation study on multi-rate three-stage Clos switchi...
In order to avoid crosstalk, a new architecture is proposed for Optical Multistage Interconnection N...
Switching elements in interconnection networks for highly parallel shared memory computer systems ma...
An interconnection network system consists of layers of switching elements connected together in a p...
SIGLECNRS-CDST / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc
Previous models for performance evaluation of multistage switches have been neither accurate enough ...
In this paper, a mathematical method for analysis of syn-chronous packet-switching interconnection n...
The optimistic analytical results for performance analysis of buffered banyan networks are mainly du...
Multistage Interconnection Networks (MIN) are used to connect processors and memories in large scale...