Design and Performance Analysis of Nanoscale Content- Addressable Memories

Abstract — This paper proposes a nanoscale content addressable memory (CAM) architecture. The type of CAM considered is adept at handling the irregular patterning of nanoscale components but requires an encoding scheme to be useful. We show how a randomly configured interface between the micro and nanoscales can accomplish this encoding. This new CAM eliminates some of the supporting microscale components required by the original crossbar architecture, at the cost of reduced storage capacity. If the projections made by Kuekes et al prove correct about the potential size of their memory, this CAM may be a valuable alternative in some applications. Index Terms — Memory architecture, memory fault tolerance, molecular electronics, nanotechnology, semiconductor devices, stochastic logic circuits, stochastic systems. I