Abstract. In this paper, we take a MIPS-based open-source uniproces-sor soft core, Plasma, and extend it to obtain the Beefarm infrastruc-ture for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in the FPGA and the computer architecture communities. We discuss various design tradeoffs and we demonstrate su-perior scalability through experimental results compared to traditional software instruction set simulators. Based on our experience of designing and building a complete FPGA-based multiprocessor emulation system that supports run-time and compiler infrastructure and on the actual executions of our experiments running Software Transactional Memory (STM) benchmarks, we comment on the pros, cons and ...
Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurabil...
Historically, there have been two methods for assessing microarchitectural ideas. Most groups use cy...
Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of deg...
In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obt...
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memo...
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memo...
In the the last decades several performance walls were hit. The memory wall and the power wall are l...
The single core processor stagnated due to four major factors. (1) The lack of instruction level par...
In this paper we discuss the development of two emulation platforms for transactional memory systems...
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it...
The use of cycle-accurate software simulators as a foundation for the exploration of all the possib...
Multi-core processors is a design philosophy that has become mainstream in scientific and engineerin...
This paper demonstrates a new hardware/software co-simulation method that performs execution-driven ...
With the growing complexity in consumer embedded products and the improvements in process technology...
This paper analyses the performance of a custom compute machine, that performs electrostatic plasma ...
Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurabil...
Historically, there have been two methods for assessing microarchitectural ideas. Most groups use cy...
Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of deg...
In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obt...
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memo...
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memo...
In the the last decades several performance walls were hit. The memory wall and the power wall are l...
The single core processor stagnated due to four major factors. (1) The lack of instruction level par...
In this paper we discuss the development of two emulation platforms for transactional memory systems...
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it...
The use of cycle-accurate software simulators as a foundation for the exploration of all the possib...
Multi-core processors is a design philosophy that has become mainstream in scientific and engineerin...
This paper demonstrates a new hardware/software co-simulation method that performs execution-driven ...
With the growing complexity in consumer embedded products and the improvements in process technology...
This paper analyses the performance of a custom compute machine, that performs electrostatic plasma ...
Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurabil...
Historically, there have been two methods for assessing microarchitectural ideas. Most groups use cy...
Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of deg...