1Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Abstract—This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates. These results can be used to guide the microarchitectural design of many structures. We focus on the microarchitecture of soft processors on FPGAs and show how soft processor microarchi-tectures should be different from those of the more extensively-studied hard processors on custom CMOS. We find that the ratios of the custom CMOS vs. FPGA area for different building blocks varies considerably more than the speed ratios. As area is often a key design constraint in FPGA circuits, area ratios have the most impact on microarchitecture choices. Complete processor cores on an FPGA use 17-27 × more area (“area ratio”) and have 18-26 × greater delay (“delay ratio”) than the same design implemented in custom CMOS. Building blocks with dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7 × area ratio), while multiplexers and content-addressable memories (CAM) are particularly area-inefficient (>100 × area ratio). We also find a low delay ratio for pipeline latches (12-19×). Applying these results, we find that FPGA soft processors should have 20 % deeper pipelines than equivalent custom CMOS processors. Soft processors can have higher capacity caches, but should avoid CAM-based fully-associative caches. Out of order soft processors should consider using physical register file organizations to minimize CAM size and RAM port counts. I