Power and performance of native and java benchmarks on 130nm to 32nm process technologies

Over the past decade, chip fabrication technology shrank from 130nm to 32nm. This reduction was generally considered to pro-vide performance improvements together with chip power reduc-tions. This paper examines how well process technology and mi-croarchitecture delivered on this assumption. This paper evalu-ates power and performance of native and Java workloads across a selection of IA32 processors from five technology generations (130nm, 90nm, 65nm, 45nm, and 32nm). We use a Hall effect sen-sor to accurately measure chip power. This paper reports a range findings in three areas. 1) Methodology: TDP is unsurprisingly a poor predictor of application power consumption for a particular processor, but worse, TDP is a poor predictor of relative power consumption between processors. 2) Power-performance trends: Processors appear to have already hit the power wall at 45nm. 3) Native versus Java workloads and their relationship to processor technology: Single threaded Java workloads exploit multiple cores. These results indicate that Java workloads offer different opportu-nities and challenges compared to native workloads. Our findings challenge prevalent methodologies and offer new insight into how microarchitectures have traded power and performance as process technology shrank. 1