Add to ORKGThis work presents a new style of gate-level reconfigurable cells based on the double-gate (DG) MOSFET device. The proposed dynamic- and static-logic cells demonstrate significant gate area reductions compared to conventional CMOS lookup table (LUT) techniques (between 80-95%) while configuration memory requirements are also reduced (up to 60%). Simulation results show that it can be used either in low power reconfigurable applications (up to 90% power reduction is possible) or for speeds comparable to those of CMOS-LUTs
Logic functions are the key backbone in electronic circuits for computing applications. Complementar...
This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbo...
Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their ...
A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed....
In this thesis, Double Gate (DG) MOSFET technology is studied and subsequently some useful applicati...
Prior work has shown that due to the overhead incurred in enabling reconfigurability, field-programm...
This dissertation describes using theory, computer simulations and laboratory measurements a new cla...
Two different CMOS transistors with a low threshold voltage, given by a commercial available 22 nm F...
Abstract A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as...
With the increasing non-recurring engineering cost of advanced process technologies, reconfigurable ...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar do...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar do...
We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was base...
Reconfigurable Circuit (RC) platforms can be configured to implement complex combinatorial and seque...
We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was base...
Logic functions are the key backbone in electronic circuits for computing applications. Complementar...
This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbo...
Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their ...
A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed....
In this thesis, Double Gate (DG) MOSFET technology is studied and subsequently some useful applicati...
Prior work has shown that due to the overhead incurred in enabling reconfigurability, field-programm...
This dissertation describes using theory, computer simulations and laboratory measurements a new cla...
Two different CMOS transistors with a low threshold voltage, given by a commercial available 22 nm F...
Abstract A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as...
With the increasing non-recurring engineering cost of advanced process technologies, reconfigurable ...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar do...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar do...
We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was base...
Reconfigurable Circuit (RC) platforms can be configured to implement complex combinatorial and seque...
We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was base...
Logic functions are the key backbone in electronic circuits for computing applications. Complementar...
This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbo...
Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their ...