White Paper Using Digital Verification Techniques on Mixed-Signal SoCs with CustomSim and VCS Authors

The traditional approach used for verification in the analog world still lacks some key aspects that have been efficiently deployed in digital verification for years. SPICE-based analog verification environments are usually hard to reuse at the system-on-chip (SoC) level, difficult to control and barely meet the required simulation performance. By leveraging the well-proven VMM and UVM methodologies, the VCS® AMS testbench technology is to provide analog designers and verification engineers with a methodology that allows them to: ` ` Introduce analog verification planning ` ` Introduce constraint-random verification for driving analog nodes ` ` Model analog stimulus as shaped transaction-based bus functional models ` ` Integrate reference models with various abstraction level ` ` Sample analog nodes to monitor incoming traffic ` ` Introduce assertions on analog nodes ` ` Introduce analog code coverage and functional coverage ` ` Introduce regression management In addition to elaborating on the above features, this white paper describes a scalable and reusable methodology for verifying analog IP. Reuse is made possible by correct modeling of verification models that can be stitched into the SoC. These models can be implemented with HDL or Verilog-AMS, depending on the required accuracy. This white paper is a case study that explains the various aspects of this methodology that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection