Analysis and Optimization of Lateral Thin-Film Silicon-on-Insulator (SOI) PMOS Transistor with an NBL layer in the Drift Region

This paper analyses the experimental results of voltage capability (VBR> 120V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 µm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structure have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteritics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transitors