Automating processor customisation: Optimised memory access and resource sharing

We propose a novel methodology to generate Appli-cation Specic Instruction Processors (ASIPs) including custom instructions. Our implementation balances perfor-mance and area requirements by making custom instruc-tions reusable across similar pieces of code. In addition to arithmetic and logic operations, table look-ups within cus-tom instructions reduce costly accesses to global memory. We present synthesis and cycle-accurate simulation results for six embedded benchmarks running on customised pro-cessors. Reusable custom instructions achieve an average 319 % speedup with only 5 % additional area. The maxi-mum speedup of 501 % for the Advanced Encryption Stan-dard (AES) requires only 3.6 % additional area. 1