Memory controller optimizations for web servers

This paper analyzes memory access scheduling and vir-tual channels as mechanisms to reduce the latency of main memory accesses by the CPU and peripherals in web servers. Despite the address filtering effects of the CPU’s cache hierarchy, there is significant locality and bank par-allelism in the DRAM access stream of a web server, which includes traffic from the operating system, application, and peripherals. However, a sequential memory controller leaves much of this locality and parallelism unexploited, as serialization and bank conflicts affect the realizable latency. Aggressive scheduling within the memory controller to exploit the available parallelism and locality can reduce the average read latency of the SDRAM. However, bank con-flicts and the limited ability of the SDRAM’s internal row buffers to act as a cache hinder further latency reduction. Virtual channel SDRAM overcomes these limitations by pro-viding a set of channel buffers that can hold segments from rows of any internal SDRAM bank. This paper presents memory controller policies that can make effective use of these channel buffers to further reduce the average read la-tency of the SDRAM.