Memory forwarding is an effective way to dynamically optimize the data layout. It provides a safe way to improve the performance of cache by actively creating better data locality. The existing memory forwarding mechanism needs additional hardware support to perform the address redirection, which greatly limits its real application. To put the memory forwarding technique into widely practice, we propose a new way of software-based implementation. Based on the fact that good data layout can bring much improvement of cache performance and actual forwarding is a rare event during the execution, our experiment shows that reasonable speedup that can be achieved by using this software-based memory forwarding technique
This paper proposes a forwarding pointer-based cache scheme (PB-Cache scheme) that can reduce the si...
On the road to computer systems able to support the requirements of exascale applications, Chip Mult...
The memory system remains a major performance bottleneck in modern and future architectures. In this...
By optimizing data layout at run-time, we can potentially en-hance the performance of caches by acti...
Scalable shared-memory multiprocessors are often slowed down by long-latency memory accesses. One wa...
Abstract As the difference in speed between processor and memory system continues to increase, it is...
In this paper, we discuss access forwarding schemes for the replication that achieve balanced access...
The performance gap between processor and memory continues to remain a major performance bottleneck ...
This dissertation considers the use of data prefetching and an alternative mechanism, data forwardin...
Commercial link : http://www.springerlink.de/ ALCHEMY/http://www.springer.comCache memories were inv...
Abstract—Packet forwarding is a memory-intensive application requiring multiple accesses through a t...
This dissertation presents a hardware accelerator that is able to accelerate large (including non-pa...
In today’s computer architectures, many scientific applications are considered to be memory bound. T...
As the gap between processor power and memory speed continues to widen, cache performance of modern ...
The performance of a traditional cache memory hierarchy can be improved by utilizing mechanisms such...
This paper proposes a forwarding pointer-based cache scheme (PB-Cache scheme) that can reduce the si...
On the road to computer systems able to support the requirements of exascale applications, Chip Mult...
The memory system remains a major performance bottleneck in modern and future architectures. In this...
By optimizing data layout at run-time, we can potentially en-hance the performance of caches by acti...
Scalable shared-memory multiprocessors are often slowed down by long-latency memory accesses. One wa...
Abstract As the difference in speed between processor and memory system continues to increase, it is...
In this paper, we discuss access forwarding schemes for the replication that achieve balanced access...
The performance gap between processor and memory continues to remain a major performance bottleneck ...
This dissertation considers the use of data prefetching and an alternative mechanism, data forwardin...
Commercial link : http://www.springerlink.de/ ALCHEMY/http://www.springer.comCache memories were inv...
Abstract—Packet forwarding is a memory-intensive application requiring multiple accesses through a t...
This dissertation presents a hardware accelerator that is able to accelerate large (including non-pa...
In today’s computer architectures, many scientific applications are considered to be memory bound. T...
As the gap between processor power and memory speed continues to widen, cache performance of modern ...
The performance of a traditional cache memory hierarchy can be improved by utilizing mechanisms such...
This paper proposes a forwarding pointer-based cache scheme (PB-Cache scheme) that can reduce the si...
On the road to computer systems able to support the requirements of exascale applications, Chip Mult...
The memory system remains a major performance bottleneck in modern and future architectures. In this...