Scalable Recongurable Channel Decoder Architecture for Future Wireless

The current trend in the consumer devices and commu-nication service provider market is the integration of dif-ferent communication standards within a single device (e.g. GSM phone with Bluetooth, WLAN and infrared interface) requiring tight integration of mobile broadcast, networking and cellular technologies within one product. Channel de-coder is traditionally one of the most computationally in-tensive building block within digital receivers. The aim of this paper is to investigate the feasibility of a programmable channel decoder that can be dynamically recongured for decoding turbo and convolutionally encoded streams from various wireless standards. The architecture options are presented and the area costs and exibility compared be-tween the options. The resulting decoder architecture sup-ports hardware resource sharing and reconguration be-tween different standards and decoders and is more efcient in terms of silicon area than independent implementation of every decoder on the same IC. 1