Compact Modeling for New Transistor Structures

Using embedded SRAM as a path, FinFET may enter manufacturing at 32nm. FinFET provides several advantages over the planar MOSFET structure----smaller size, larger current, smaller leakage, and less variation in threshold voltage. A compact model of multi-gate transistors will facilitate their adoption. BSIM-MG is a surface-potential based compact model of multi-gate MOSFETs fabricated on either SOI or bulk substrates. The effects of body doping are modeled. It can also model a double-gate transistor with independently biased front and back gates and asymmetric front and back gate work-functions and dielectric thicknesses. 1 Advantages of FinFET over Planar MOSFET What makes a transistor different from a resistor is that the gate controls the conduction channel, not the drain. The gate exerts its control through capacitive (electrostatic) coupling to the channel. When we shrink the MOSFET gate to a smaller size, the drain is pulled closer to the (middle of the) channel. That increases the capacitive coupling between the drain and the channel. When the transistor is too small, the drain has enough coupling to the channel that a current (leakage current) flows with only a drain voltage applied without a gate voltage. This is the problem facing the planar transistor structure, which has not changed for four decades. FinFET [1] allows the gate to control the channel from several sides (see Fig.1), thus increasing the gate control and allows the gate length to be reduced further. Since the introduction of FinFET, this structure has been used to set new world record of smallest gate length several times at various research laboratories. The current record is 3nm gate length. Clearly, FinFET can serve many technology nodes