A Low-Leakage Twin-Precision Multiplier Using Recongurable Power Gating

Abstract A twin-precision multiplier that uses recongurable power gating is presented. Employing power cut-off techniques in independently controlled power-gating regions, yields signicant static leakage reductions when half-precision multiplications are carried out. In comparison to a conventional 8-bit tree multi-plier, the power overhead of a 16-bit twin-precision multiplier operating at 8-bit precision has been reduced by 53 % when recongurable power gating based on the SCCMOS power cut-off technique was applied. I