ESD Protection Design for High-Speed I/O Interface Circuit

National Chiao-Tung University This thesis focuses on the ESD protection design for high-speed input/output (I/O) interface circuit. The gate oxide of the MOSFET transistor becomes thinner as the CMOS technology scales, which enables the high-speed I/O interface circuits with higher operating frequency. Unfortunately, there exists a challenge to design an ESD protection circuit with satisfactory ESD robustness and low parasitic effects to the gigahertz high-speed I/O circuit. This thesis presents a design methodology to design the ESD protection circuit for gigahertz high-speed I/O circuits with high ESD robustness and low parasitic capacitance. There are two major designs in this thesis, in first part, the two-port ground-signal-ground (GSG) measurement setup in the radio-frequency band (~GHz) is used to measure the high-frequency characteristics of ESD devices and the TLP measurement system is used to measure the ESD robustness of the ESD devices in a 0.13-μm CMOS process. Therefore, the relationship between the high-frequenc