Top-Gated Silicon Nanowire Transistors in a Single Fabrication Step

he growing research in silicon nanowires (SiNWs) for nanoelectron-ics applications has resulted in sev-eral NW-based devices, such as pn junctions,1,2 inversion- or accumulation-mode field-effect transistors (FETs),37 and tunneling FETs.2 Top-gated FET geometries, in particular, are crucial to probe the electri-cal properties of SiNWs because they allow stronger gate coupling when compared to back-gated devices.2,711 However, pattern-ing metal electrodes as FET terminals (source, drain, and gate) on top of a SiNW inevitably requires two lithography steps. After the preparation of source and drai