FPGA IMPLEMENTATION OF IP PROTECTION THROUGH VISUAL INFORMATION HIDING

IP based design is one of the most potential techniques to promote the SoC design promptly into market. To assist the process it is advantageous to have IP exchanged in different forms. Though, sharing IP blocks in today’s aggressive market poses significant security risks. Proving that a given IP is derived from a patented method or technique is in general a conscientiously time-consuming task, often requiring reverse-engineering and forensic investigation of IP. These techniques are so multifaceted that their uses to a huge collection of marketable products are almost always unaffordable. So protection of IPs in VLSI design has received a deal of interest in recent era. In this paper, we present an approach based on the embedding of the ownership proof as part of the IP design’s finite state machine (FSM) by means of visual information hiding