High performance reconfigurable computing for Cholesky decomposition

ABSTRACT — This paper proposes a hardware accelerator for Cholesky decomposition on FPGAs by designing a single triangular linear equation solver. Good performance is achieved by reordering the computation of Cholesky factorization algorithms and thus alleviating the data dependency. The dedicated hardware architecture for solving triangular linear equations is designed and implemented for different accuracy requirements using customized precisions. Compared to the software on the Intel Xeon quad core microprocessor, our design achieves a speedup of 7~13. I