Figure 1. a Method of uniaxial strains on MOSFETs, b TEMs of LeffTemperature Effects of n-M

partm stress nce fo the ch niaxia 121 A receiv TEMs of 40 nm gate length n-MOSFET are shown in Fig. 1b. The e Let 0.00 ©devices were patterned with 193 nm lithography. The standard pro-cesses of STI, gate oxide, SiN spacer, source/drain S/D implant, spike anneal, Ni salicide, and Cu interconnect processes were ap-plied. During gate oxide formation, nitride treatment was added. At the end of the process flow, a highly tensile silicon nitride layer was deposited, which covered the source, drain, and gate stack. This capping layer created tensile stresses in the channel area. The gate oxynitride thickness was 1.2 nm and gate polysilicon thickness was 98.5 nm. The sidewall spacer was O/N/O structure. The un-strained devices without a nitride layer were also fabricated. The transport properties of electrons in unstrained and strained Si were studied along the crystallographic 100 directions in the linear re-gime. The mechanical stress was applied in parallel or perpen-dicular direction to the MOSFET current flow. We chose this coor-dinate system versus one aligned to 100 axes. Followed are descriptions of the proposed method Fig. 1. Square strips were cut from the wafer using the saw procedure. They were abraded from a thickness of 800 to 50 m and then placed on stainless steel foil, then pasted on an aluminum pedestal with a curvature of radius 2, 3, 4, and 5 mm, using adhesive tapes. The adhesive tape is heatproo