Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects

LGR (Logic Gates as Repeaters) – a new methodology for delay optimization of SOC design with RC interconnects is described. Traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing the existing logic gates over interconnect lines, thus reducing the number of additional logically useless inverters. The application methodology of LGR is presented. Several logic circuits have been optimized by LGR and verified for delay and power. Analytical and simulated results were obtained, showing up to 25 % improvement in performance, compared with traditional repeater insertion technique. 1