Prototype of the Muon Sorter Board for the CSC Track Finder at CMS

The Cathode Strip Chamber (CSC) detector [1] at the CMS experiment at CERN consists of trapezoidal 6-layer chambers located in the endcap regions of the CMS. Ultimately, the CSC system is needed for precise muon identification (position and timing) and generation of trigger primitives for the Level-1 trigger system. Up to three trigger primitives can be send from each CSC sector (comprising 8 or 9 chambers) to the Track Finder (TF) crate located in the underground counting room. The second generation of the TF has twelve Sector Processors (SP) [2] and can accept up to 180 trigger patterns (called “muons ” later in this paper) every 25 ns from the CSC peripheral electronics. The SP computes the transverse momentum, pseudo-rapidity and azimuthal angle of each muon and sends its data (up to three muons each) to the CSC Muon Sorter (MS) that resides in the middle of the TF crate. The MS selects the four best candidates out of 36 possible and transmits them in ranked order to the Global Muon Trigger (GMT) for further processing. Our initial approach to MS design and results of simulation were presented at the 6th and 7th Workshops on Electronics for LHC Experiments [3-4]. The design is based on a single programmable logic device that provides all the necessary board functions. Some improvements were made in the past two years. Particularly, we decided to switch from an Altera PLD to Xilinx FPGA and use a common with the SP mezzanine card that carries the Virtex-2 FPGA and associated EPROM’s. Hopefully, both the SP and MS designs require about the same number of input/output pins and internal resources for the main mezzanine-based FPGA. Due to optimization of the sorter logic, advances in FPGA technology and design software (Xilinx ISE 5.1) we were able to reduce the latency of sorting comparing to our previous estimate. The results of the FPGA design, board prototyping and initial tests are presented below