Characterisation of FPGA clock variability

As integrated circuits are scaled down it becomes dif-ficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic over-design. A quantified understanding of the contribution dif-ferent circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FP-GAs based on a novel differential delay measurement cir-cuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation. 1