Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications

Abstract. An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (µm/µm) in a 0.35-µm silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1 % variation), even if the analog input signal has a dynamic range of 1 V. Key Words: electrostatic discharge (ESD), ESD protection circuit, input capacitance, analog pin 1