zur Erlangung des Grades

For many numerical codes the transport of data from main memory to the registers is com-monly considered to be the main limiting factor to achieve high performance on present micro architectures. This fact is referred to as the memory wall. A lot of research is targeting this point on different levels. This covers for example code transformations and architecture aware data structures to achieve an optimal usage of the memory hierarchy found in all present micro architectures. This work shows that on modern micro architectures it is necessary to also take the requirements of the Single Instruction Multiple Data (SIMD) programming paradigm and data prefetching into account to reach high efficiencies. In this thesis the chain from high level algorithmic optimizations over the code generation process involving the compiler and the limitations and influences of the instruction set archi-tecture down to the micro architecture of the underlying hardware are analyzed. As a result we present a strategy to achieve a high efficiency for memory bandwidth limited algorithms on modern architectures. The success of this strategy is shown on the algorithmic class of grid based numerical linear equation solvers: A 2D Red-Black Gauss-Seidel smoother imple