Reducing power consumption of CMOS VLSI’s through Vdd and VT

Lowering operating voltage, VDD, is a key to low-power CMOS digital VLSI's. In order to complete a certain task in a required time and in order to keep leakage current within a tolerable level in the low VDD designs, VDD and VTH control is obligatory. This talk will cover several of the schemes including multi-VTH, variable VTH, multi-VDD and variable VDD to achieve low-power systems. Circuit level ideas to software related research are described. 1