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This paper presents a simulation study of an input buffered Asynchronous Transfer Mode (ATM) switch running the Request-Grant-Status (RGS) iterative scheduling algorithm. The RGS algorithm can reduce the effects of head-of-line blocking on the throughput and delay performance of an input buffered ATM switch. During a cell slot interval, the RGS algorithm performs a fixed number (n) of iterations. At each iteration step, the RGS algorithm determines a match between buffered cells and corresponding idle output ports. After the last iteration step, all matched cells are routed through the switch fabric. The simulation results show that the RGS algorithm can significantly improve the throughput and delay performance of an input buffered ATM switch under a high load. When independent and identical Bernoulli traffic sources are used, the input queues of a 16x16 ATM switch, using a strict first-in first-out queueing discipline, saturate at an offered load of approximately 60%. When the RGS algorithm is used with 5 iterations, the input queues of a 16x16 input buffered switch, under the same traffic conditions, d