Outline Problems with present models Review of common models Clock Synthesis Results 2

The most prevalent model is the Elmore delay model, a first order RC delay. At high frequencies the inductance of the lines plays a greater role. Many better models have been proposed but have only be used in analysis on uniform structures such as H-Trees Modern design does not use such simplified design. 3 Problems with Present Models High-frequency designs now use clock grids which require substantial routing resources and large drivers consuming a great deal of power. In exchange for these design losses, skew and jitter are amortized across the chip and manufacturing error is more tolerable 4 Review of common models Lumped C model For short local wires the capacitance of the wire is the most dominating factor, and it is reasonable to assume that the resistance and inductance are negligible RC Model (Elmore model) Overestimates downstream capacitance This error grows the larger the number of steps from the roo