SIMULATION OF SEMICONDUCTOR DEVICES AND PROCESSES Vol. 4 Edited by W. Fichtner, D. Aemmer- Zurich (Switzerland) September 12-14,1991- Hartung-Gorre Massively Parallel Computation for Three-Dimensional Monte Carlo Semiconductor Device Simulation

This work presents a study of the applicability of a massively parallel computing paradigm to Monte Carlo techniques for device simulation. A unique mapping of Monte Carlo to SIMD fine-grained parallelism has been developed, decoupling the problem into separate compu-tational domains. For MOSFET simulation, this novel mapping allows estimated speeds of over 200,000 scatterings processed per second on a 65,536 processor Connection Machine, nearly a factor of six over the fastest known to date.