Impact Ionization MOS (I-MOS)-Part I: Device and Circuit Simulations

Abstract—One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and ON 1mA m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS exper-imental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices. Index Terms—Avalanche, avalanche photodiode (APD), gate control of impact ionization, impact-ionization avalanche transit-time (IMPATT), germanium, hot carriers, impact-ionization (I-MOS), kT/q, low static power, modulated break-down, MOSFET, nonlinearity, p-i-n, silicon, subthreshold slope, 5 mV/dec