A NOVEL METHOD FOR ACHIEVING VERY LOW COPS IN CZ WAFERS

INTRODUCTION: As the IC industry moves toward development of future technology nodes and application of new materials, more innovation is required at the wafer substrate level. The silicon-on-insulator (SOI) technology will be a key factor in extending planar CMOS technologies beyond sub-50nm gate sizes. Many of the process and materials constrains facing continuous device scaling are relaxed or removed for devices fabricated on SOI wafers. The SOI is under consideration for the last three decades. The SOI based devices were first developed for spac