Efficient O n ( ) BIST Algorithms for DDNPS Faults in Dual Port Memories

The testability problem of dual port memories is investigated. Architectural modifications to enhance the testability by allowing multiple access of memory cells with minimal overhead on both silicon area and device performance are described. New fault models are proposed and efficient O ( n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhoo