A dynamically adaptive DSP for heterogeneous reconfigurable platforms

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suit-able for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technol-ogy. The most relevant features offered by the proposed architecture with respect to state of the art are zero over-head for switching between successive configurations, rel-evant area and energy computational density on compu-tational kernels (average of 2 GOPS/mm2, 0.2GOPS/mW) and relatively small area occupation (18 mm2), making it suitable for acceleration or upgrade of multi-core heteroge-neous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages. 1