Combination of SECDED with a redundancy technique can effectively tolerate a high variation-induced defect rate in future processes. However, while a defective cell in a block can be repaired by SECDED, the block becomes vul-nerable to soft errors. This paper proposes a technique to deal with the degraded resilience against soft errors. Only clean data can be stored in defective blocks of a cache. This constraint is enforced through selective write-through mechanism. An error occurring in a defective block can be detected and the correct data can be obtained from the lower level caches.
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Abstract—This paper proposes a new fault tolerant cache organ-ization capable of dynamically mapping...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the compone...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
Continuous technology scaling has brought us to a point, where transistors have become extremely sus...
Abstract—With advances in process technology, soft errors are becoming an increasingly critical desi...
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the compone...
Abstract Exponentially increasing with technology scaling, soft errors have become a serious design ...
Soft Errors are becoming a major concern for modern computing systems. Memories are one of the eleme...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
Yield improvement through exploiting fault-free sections of defective chips is a well-known techniqu...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Abstract—This paper proposes a new fault tolerant cache organ-ization capable of dynamically mapping...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the compone...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
Continuous technology scaling has brought us to a point, where transistors have become extremely sus...
Abstract—With advances in process technology, soft errors are becoming an increasingly critical desi...
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the compone...
Abstract Exponentially increasing with technology scaling, soft errors have become a serious design ...
Soft Errors are becoming a major concern for modern computing systems. Memories are one of the eleme...
Cache memory is a fundamental component of all modern microprocessors. Caches provide for efficient ...
Yield improvement through exploiting fault-free sections of defective chips is a well-known techniqu...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Abstract—This paper proposes a new fault tolerant cache organ-ization capable of dynamically mapping...