Low Pin-count Debug Interfaces for Multi-device Systems

Boundary-Scan Architecture (JTAG) is widely used as a debug interface, providing a path for a debugger to access debug com-ponents in complex systems-on-chip (SoCs). By its very nature JTAG accommodates systems containing multiple devices. How-ever, JTAG was primarily intended as a component and board test interface, and is not ideally suited as a debug interface. Its shortcomings have led the industry to search for an alternative. As a result, JTAG interfaces have started to be displaced by dedicated debug interfaces. This paper examines some of these alternatives, and concludes that a dedicated serial wire debug interface can be delivered with lower pin-count and higher per-formance, whilst maintaining support for multi-device systems and interoperability with test. I