Parity Generation and Validation for the Virtex-II Series

trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is. " By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Summary In data transmission systems the transmission channel itself is a source of data error. Hence the need to determine the validity of transmitted and received data. Parity generation and validation is a scheme to provide single bit error detection capabilities. This application note describes how to generate and validate parity in a design using the Virtex™-II architectural features including the Block SelectRAM memory in the Virtex-II series, including the Virtex-II Pro ™ devices. Introduction The validity of data is essential in applications where data is transmitted over long distances. Invalid data is a corruption risk. Parity generation helps in checking the validity of the data. This application note explains how parity is efficiently generated using the block RAM feature available in Virtex-II devices. Logic resource utilization is minimized since the data busses i