Summary

Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with significant run times. Two parallel models for GA are presented for VLSI cell placement where the objectives axe optimizing power dissipation, timing performance and interconnect wirelength, while layout width is a constraint. A Master-Slave approach is mentioned wherein both fitness calculation and crossover mechanism are distributed among slaves. A Multi-Deme parallel GA is also presented in which each processor works independently on an allocated subpopulation followed by information exchange through migration of chromosomes. A pseudo-diversity approach is taken, wherein similar solutions with the same overall cost values are not permitted in the population at any given time. A series of experiments are performed on ISCAS-85/89 benchmarks to show the performance of the Multi-Deme approach