Implementation of Digital Circuits Using Neuro- Swarm Based on FPGA 1

doi: 10.4156/ijact.vol2.issue2.6 This paper constructs fully parallel NN hardware realization of Artificial Neural Network (ANN) depends on the efficient execution of single neuron. Field Programmable Gate Array (FPGA) reconfigurable computing architecture is appropriated for hardware achievement of ANN. Numerous implementation of ANNs have been reported in scientific documents, trying to reduce Neural Networks NNs hardware circuitry. This paper constructs fully parallel NN hardware architecture reduces neuron hardware to perform an efficient NN through two main parts; the first part covers network training using Particle Swarm Optimization (PSO) modified MATLAB tools utilized of PSO advantages, the second part represents the hardware implementation of the trained network through Xilinx high performance Virtex FPGA schematic entry design tools