Quantitative Comparison of Different Design Approaches for FPGA-based Design Flows

The complexity of modern PLDs and FPGAs is in-cessantly increasing. Multi-context and 2-million-gates devices require new design techniques to be established. Design reuse is one of the approaches trying to address this additional complexity. Previous works on reuse were focused on IP definition and parameterization as well as databases for IP management. This paper de-scribes a study of different design specification tech-niques compared with dedicated (non-reusable) design flows. The results are summarized in terms of timing data and cell complexity for Altera FLEX 10K and Xil-inx XC4000 FPGAs. It turns out, that different pos-sibilities of design entry result in wide spread of de-sign performance data depending on the circuit class (FSM, combinational or registered logic). The chosen test suite suggests that designs specified in platform-independent VHDL needs on average 41 % more logic resources and achieves 17 % worse timing than their non-reusable counterparts.