OCP compliant JTAG controller- IP core

Abstract – Boundary-scan, formally known as IEEE 1149.1-2001, is a collection of design rules applied at Integrated Circuit (IC) level that allows standardized approaches of testing the IC internally and at board level. The current approach for designing an integrated circuit as SoC (System-on-Chip) is based on the reusing the model for a very well defined block. This paper presents an reusable IP core that has two standard interfaces: JTAG interface for testing and standardized access purpose and OCP interface that facilitates "plug and play " SoC design. This design has been checked in synthesis and proved by several ASIC implementations